)]}'
{
  "commit": "ec8843513e6083b188c0498f076b837a4e3cd670",
  "tree": "5a64c010a74a671c1b62c968dbf3cfccbe64fb67",
  "parents": [
    "3b962ad83021a935fa7cc8dfef7c40b1d7c215d4"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Mar 07 16:00:48 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Mar 08 11:28:54 2023 +0100"
  },
  "message": "systemverilog-plugin: simplify module processing\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5f9d2fc124e234f66fb2324fd1b7d6975d428fa6",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "356e424b38a9a67b6d287a64d7f1065f51086635",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}