commit eeab159e0f1055399105f1f8b082e3004c4d12ea
author Maciej Kurc <mkurc@antmicro.com> Tue Aug 03 14:29:22 2021 +0200
committer Maciej Kurc <mkurc@antmicro.com> Mon Aug 23 10:41:42 2021 +0200
tree a6fe3507df4fef5c1bc56e959ca8df871782c1a1
parent 56d926e44b429d41533e38b891dbeac5b37a538a

Added reading library cell definitions in synth_quicklogic with -nomem2reg option.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

ql-qlf-plugin/synth_quicklogic.cc

diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 36c3afe..241005d 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -192,7 +192,10 @@
             std::string readVelArgs;
             readVelArgs = " +/quicklogic/" + family + "/cells_sim.v";
 
-            run("read_verilog -lib -specify +/quicklogic/common/cells_sim.v" + readVelArgs);
+            // Use -nomem2reg here to prevent Yosys from complaining about
+            // some block ram cell models. After all the only part of the cells
+            // library required here is cell port definitions plus specify blocks.
+            run("read_verilog -lib -specify -nomem2reg +/quicklogic/common/cells_sim.v" + readVelArgs);
             run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
         }