diff --git a/.github/workflows/build-and-test.sh b/.github/workflows/build-and-test.sh
new file mode 100755
index 0000000..8fd95f9
--- /dev/null
+++ b/.github/workflows/build-and-test.sh
@@ -0,0 +1,25 @@
+#! /bin/bash
+
+set -e
+
+source .github/workflows/common.sh
+
+##########################################################################
+
+start_section Building
+make plugins -j`nproc`
+end_section
+
+##########################################################################
+
+start_section Installing
+make install -j`nproc`
+end_section
+
+##########################################################################
+
+start_section Testing
+make test -j`nproc`
+end_section
+
+##########################################################################
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
new file mode 100644
index 0000000..42f5810
--- /dev/null
+++ b/.github/workflows/ci.yml
@@ -0,0 +1,31 @@
+name: CI tests
+
+on: [push, pull_request]
+
+jobs:
+
+  Run-tests:
+    runs-on: ubuntu-latest
+    steps:
+
+    - uses: actions/checkout@v2
+
+    - uses: actions/setup-python@v2
+
+    - name: Install
+      run: |
+        sudo apt-get update
+        sudo apt-get install git g++-9 build-essential bison flex \
+          libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot \
+          pkg-config libboost-system-dev libboost-python-dev \
+          libboost-filesystem-dev zlib1g-dev
+
+    - name: Install Yosys
+      run: source .github/workflows/setup.sh
+      env:
+        OS: ${{ runner.os }}
+
+    - name: Build and test plugins
+      run: source .github/workflows/build-and-test.sh
+      env:
+        OS: ${{ runner.os }}
diff --git a/.github/workflows/common.sh b/.github/workflows/common.sh
new file mode 100644
index 0000000..53e7033
--- /dev/null
+++ b/.github/workflows/common.sh
@@ -0,0 +1,39 @@
+#! /bin/bash
+
+# Look for location binaries first
+export PATH="$HOME/.local-bin/bin:$PATH"
+
+# OS X specific common setup
+if [[ "${OS}" == "macOS" ]]; then
+	export PATH="/usr/local/opt/ccache/libexec:$PATH"
+fi
+
+# Parallel builds!
+MAKEFLAGS="-j 2"
+
+function action_fold() {
+	if [ "$1" = "start" ]; then
+		echo "::group::$2"
+		SECONDS=0
+	else
+		duration=$SECONDS
+		echo "::endgroup::"
+		printf "${GRAY}took $(($duration / 60)) min $(($duration % 60)) sec.${NC}\n"
+	fi
+	return 0;
+}
+
+function start_section() {
+	action_fold start "$1"
+	echo -e "${PURPLE}SymbiFlow Yosys Plugins${NC}: - $2${NC}"
+	echo -e "${GRAY}-------------------------------------------------------------------${NC}"
+}
+
+export -f start_section
+
+function end_section() {
+	echo -e "${GRAY}-------------------------------------------------------------------${NC}"
+	action_fold end "$1"
+}
+
+export -f end_section
diff --git a/.github/workflows/setup.sh b/.github/workflows/setup.sh
new file mode 100755
index 0000000..abe6e8d
--- /dev/null
+++ b/.github/workflows/setup.sh
@@ -0,0 +1,54 @@
+#! /bin/bash
+
+set -e
+
+source .github/workflows/common.sh
+
+##########################################################################
+
+# Output status information.
+start_section Status
+(
+    set +e
+    set -x
+    git status
+    git branch -v
+    git log -n 5 --graph
+    git log --format=oneline -n 20 --graph
+)
+end_section
+
+##########################################################################
+
+# Update submodules
+start_section Submodules
+(
+    git submodule update --init --recursive
+)
+end_section
+
+##########################################################################
+
+#Install yosys
+start_section Install-Yosys
+(
+    if [ ! -e ~/.local-bin/bin/yosys ]; then
+        echo '=========================='
+        echo 'Building yosys'
+        echo '=========================='
+        mkdir -p ~/.local-src
+        mkdir -p ~/.local-bin
+        cd ~/.local-src
+        git clone https://github.com/SymbiFlow/yosys.git -b master+wip
+        cd yosys
+        PREFIX=$HOME/.local-bin make -j$(nproc)
+        PREFIX=$HOME/.local-bin make install
+        echo $(which yosys)
+        echo $(which yosys-config)
+        echo $(yosys-config --datdir)
+    fi
+)
+end_section
+
+##########################################################################
+
diff --git a/.travis.yml b/.travis.yml
deleted file mode 100644
index 58b379e..0000000
--- a/.travis.yml
+++ /dev/null
@@ -1,49 +0,0 @@
-sudo: false
-language: cpp
-
-#cache:
-# ccache: false
-# directories:
-#  - ~/.local-bin
-
-
-env:
-  global:
-    - MAKEFLAGS="-j 2"
-
-include:
-  # Latest gcc supported on Travis Linux
-  - os: linux
-    addons:
-      apt:
-        sources:
-          - ubuntu-toolchain-r-test
-        packages:
-          - g++-9
-          - gperf
-          - build-essential
-          - bison
-          - flex
-          - libreadline-dev
-          - gawk
-          - tcl-dev
-          - libffi-dev
-          - git
-          - graphviz
-          - xdot
-          - pkg-config
-          - python
-          - python3
-          - libboost-system-dev
-          - libboost-python-dev
-          - libboost-filesystem-dev
-          - zlib1g-dev
-    env:
-      - MATRIX_EVAL="CONFIG=gcc && CC=gcc-9 && CXX=g++-9"
-
-before_install:
-  - ./.travis/setup.sh
-
-script:
-  - ./.travis/build-and-test.sh
-
diff --git a/.travis/build-and-test.sh b/.travis/build-and-test.sh
deleted file mode 100755
index e1cd5df..0000000
--- a/.travis/build-and-test.sh
+++ /dev/null
@@ -1,61 +0,0 @@
-#! /bin/bash
-
-set -e
-
-source .travis/common.sh
-
-##########################################################################
-
-echo
-echo 'Configuring...' && echo -en 'travis_fold:start:script.configure\\r'
-echo
-
-if [ "$CONFIG" = "gcc" ]; then
-	echo "Configuring for gcc."
-	make config-gcc
-elif [ "$CONFIG" = "clang" ]; then
-	echo "Configuring for clang."
-	make config-clang
-fi
-
-echo
-echo -en 'travis_fold:end:script.configure\\r'
-echo
-
-##########################################################################
-
-echo
-echo 'Building plugins..' && echo -en 'travis_fold:start:script.build\\r'
-echo
-
-make plugins -j`nproc`
-
-echo
-echo -en 'travis_fold:end:script.build\\r'
-echo
-
-##########################################################################
-
-echo
-echo 'Installing plugins...' && echo -en 'travis_fold:start:script.build\\r'
-echo
-
-make install -j`nproc`
-
-echo
-echo -en 'travis_fold:end:script.build\\r'
-echo
-
-##########################################################################
-
-echo
-echo 'Testing...' && echo -en 'travis_fold:start:script.test\\r'
-echo
-
-make test -j`nproc`
-
-echo
-echo -en 'travis_fold:end:script.test\\r'
-echo
-
-##########################################################################
diff --git a/.travis/common.sh b/.travis/common.sh
deleted file mode 100644
index 8eecc4c..0000000
--- a/.travis/common.sh
+++ /dev/null
@@ -1,15 +0,0 @@
-#! /bin/bash
-
-# Setup the CC / CXX from the matrix config
-eval "${MATRIX_EVAL}"
-
-# Look for location binaries first
-export PATH="$HOME/.local-bin/bin:$PATH"
-
-# OS X specific common setup
-if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
-	export PATH="/usr/local/opt/ccache/libexec:$PATH"
-fi
-
-# Parallel builds!
-MAKEFLAGS="-j 2"
diff --git a/.travis/setup.sh b/.travis/setup.sh
deleted file mode 100755
index 3416017..0000000
--- a/.travis/setup.sh
+++ /dev/null
@@ -1,47 +0,0 @@
-#! /bin/bash
-
-set -e
-
-source .travis/common.sh
-
-##########################################################################
-
-# Output status information.
-(
-	set +e
-	set -x
-	git status
-	git branch -v
-	git log -n 5 --graph
-	git log --format=oneline -n 20 --graph
-)
-echo
-echo -en 'travis_fold:end:before_install.git\\r'
-echo
-
-##########################################################################
-
-#Install yosys
-(
-        if [ ! -e ~/.local-bin/bin/yosys ]; then
-                echo
-                echo 'Building yosys...' && echo -en 'travis_fold:start:before_install.yosys\\r'
-                echo
-                mkdir -p ~/.local-src
-                mkdir -p ~/.local-bin
-                cd ~/.local-src
-                git clone https://github.com/SymbiFlow/yosys.git -b master+wip
-                cd yosys
-                PREFIX=$HOME/.local-bin make -j$(nproc)
-                PREFIX=$HOME/.local-bin make install
-                echo $(which yosys)
-                echo $(which yosys-config)
-                echo $(yosys-config --datdir)
-                echo
-                echo -en 'travis_fold:end:before_install.yosys\\r'
-                echo
-        fi
-)
-
-##########################################################################
-
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.golden.txt b/design_introspection-plugin/tests/get_cells/get_cells.golden.txt
index d33818d..b6ff53b 100644
--- a/design_introspection-plugin/tests/get_cells/get_cells.golden.txt
+++ b/design_introspection-plugin/tests/get_cells/get_cells.golden.txt
@@ -12,4 +12,4 @@
 OBUFTDS_2
 
 All cells
-{$abc$2135$lut$not$aiger2134$1} {$auto$alumacc.cc:485:replace_alu$1469.slice[0].carry4_1st_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[0].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[1].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[1].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[2].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[2].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[3].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[3].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[4].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[4].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[5].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[5].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[6].carry4_part} {$auto$simplemap.cc:420:simplemap_dff$1476} {$auto$simplemap.cc:420:simplemap_dff$1477} {$auto$simplemap.cc:420:simplemap_dff$1478} {$auto$simplemap.cc:420:simplemap_dff$1479} {$auto$simplemap.cc:420:simplemap_dff$1480} {$auto$simplemap.cc:420:simplemap_dff$1481} {$auto$simplemap.cc:420:simplemap_dff$1482} {$auto$simplemap.cc:420:simplemap_dff$1483} {$auto$simplemap.cc:420:simplemap_dff$1484} {$auto$simplemap.cc:420:simplemap_dff$1485} {$auto$simplemap.cc:420:simplemap_dff$1486} {$auto$simplemap.cc:420:simplemap_dff$1487} {$auto$simplemap.cc:420:simplemap_dff$1488} {$auto$simplemap.cc:420:simplemap_dff$1489} {$auto$simplemap.cc:420:simplemap_dff$1490} {$auto$simplemap.cc:420:simplemap_dff$1491} {$auto$simplemap.cc:420:simplemap_dff$1492} {$auto$simplemap.cc:420:simplemap_dff$1493} {$auto$simplemap.cc:420:simplemap_dff$1494} {$auto$simplemap.cc:420:simplemap_dff$1495} {$auto$simplemap.cc:420:simplemap_dff$1496} {$auto$simplemap.cc:420:simplemap_dff$1497} {$auto$simplemap.cc:420:simplemap_dff$1498} {$auto$simplemap.cc:420:simplemap_dff$1499} {$auto$simplemap.cc:420:simplemap_dff$1500} {$auto$simplemap.cc:420:simplemap_dff$1501} {$iopadmap$top.clk} OBUFTDS_2 OBUF_6 OBUF_7 OBUF_OUT bottom_inst.OBUF_10 bottom_inst.OBUF_11 bottom_inst.OBUF_9 bottom_intermediate_inst.OBUF_8
+{$abc$1984$lut$not$aiger1983$1} {$auto$alumacc.cc:485:replace_alu$1385.slice[0].carry4} {$auto$alumacc.cc:485:replace_alu$1385.slice[1].carry4} {$auto$alumacc.cc:485:replace_alu$1385.slice[2].carry4} {$auto$alumacc.cc:485:replace_alu$1385.slice[3].carry4} {$auto$alumacc.cc:485:replace_alu$1385.slice[4].carry4} {$auto$alumacc.cc:485:replace_alu$1385.slice[5].carry4} {$auto$alumacc.cc:485:replace_alu$1385.slice[6].carry4} {$auto$simplemap.cc:420:simplemap_dff$1471} {$auto$simplemap.cc:420:simplemap_dff$1472} {$auto$simplemap.cc:420:simplemap_dff$1473} {$auto$simplemap.cc:420:simplemap_dff$1474} {$auto$simplemap.cc:420:simplemap_dff$1475} {$auto$simplemap.cc:420:simplemap_dff$1476} {$auto$simplemap.cc:420:simplemap_dff$1477} {$auto$simplemap.cc:420:simplemap_dff$1478} {$auto$simplemap.cc:420:simplemap_dff$1479} {$auto$simplemap.cc:420:simplemap_dff$1480} {$auto$simplemap.cc:420:simplemap_dff$1481} {$auto$simplemap.cc:420:simplemap_dff$1482} {$auto$simplemap.cc:420:simplemap_dff$1483} {$auto$simplemap.cc:420:simplemap_dff$1484} {$auto$simplemap.cc:420:simplemap_dff$1485} {$auto$simplemap.cc:420:simplemap_dff$1486} {$auto$simplemap.cc:420:simplemap_dff$1487} {$auto$simplemap.cc:420:simplemap_dff$1488} {$auto$simplemap.cc:420:simplemap_dff$1489} {$auto$simplemap.cc:420:simplemap_dff$1490} {$auto$simplemap.cc:420:simplemap_dff$1491} {$auto$simplemap.cc:420:simplemap_dff$1492} {$auto$simplemap.cc:420:simplemap_dff$1493} {$auto$simplemap.cc:420:simplemap_dff$1494} {$auto$simplemap.cc:420:simplemap_dff$1495} {$auto$simplemap.cc:420:simplemap_dff$1496} {$iopadmap$top.clk} OBUFTDS_2 OBUF_6 OBUF_7 OBUF_OUT bottom_inst.OBUF_10 bottom_inst.OBUF_11 bottom_inst.OBUF_9 bottom_intermediate_inst.OBUF_8
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.tcl b/design_introspection-plugin/tests/get_cells/get_cells.tcl
index 861e6a9..85cc897 100644
--- a/design_introspection-plugin/tests/get_cells/get_cells.tcl
+++ b/design_introspection-plugin/tests/get_cells/get_cells.tcl
@@ -5,7 +5,7 @@
 
 read_verilog get_cells.v
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 
 set fp [open "get_cells.txt" "w"]
diff --git a/design_introspection-plugin/tests/get_nets/get_nets.golden.txt b/design_introspection-plugin/tests/get_nets/get_nets.golden.txt
index 24c2e2f..34eb615 100644
--- a/design_introspection-plugin/tests/get_nets/get_nets.golden.txt
+++ b/design_introspection-plugin/tests/get_nets/get_nets.golden.txt
@@ -7,4 +7,4 @@
 Filtered nets
 clk
 All nets
-{$abc$2135$aiger2134$38} {$abc$2135$aiger2134$42} {$abc$2135$aiger2134$43} {$abc$2135$aiger2134$48} {$abc$2135$aiger2134$49} {$abc$2135$aiger2134$54} {$abc$2135$aiger2134$55} {$abc$2135$aiger2134$60} {$abc$2135$aiger2134$61} {$abc$2135$aiger2134$66} {$abc$2135$aiger2134$67} {$abc$2135$aiger2134$72} {$abc$2135$aiger2134$73} {$abc$2135$aiger2134$76} {$abc$2135$aiger2134$77} {$abc$2135$aiger2134$78} {$abc$2135$iopadmap$clk} {$auto$alumacc.cc:485:replace_alu$1469.O} LD6 LD7 LD8 LD9 bottom_inst.I bottom_inst.O bottom_inst.OB bottom_intermediate_inst.I bottom_intermediate_inst.O bottom_intermediate_inst.bottom_intermediate_wire clk counter inter_wire inter_wire_2 led out_a out_b signal_n signal_p
+{$abc$1984$aiger1983$38} {$abc$1984$aiger1983$42} {$abc$1984$aiger1983$43} {$abc$1984$aiger1983$44} {$abc$1984$aiger1983$45} {$abc$1984$aiger1983$50} {$abc$1984$aiger1983$51} {$abc$1984$aiger1983$52} {$abc$1984$aiger1983$53} {$abc$1984$aiger1983$58} {$abc$1984$aiger1983$59} {$abc$1984$aiger1983$60} {$abc$1984$aiger1983$61} {$abc$1984$aiger1983$66} {$abc$1984$aiger1983$67} {$abc$1984$aiger1983$68} {$abc$1984$aiger1983$69} {$abc$1984$aiger1983$74} {$abc$1984$aiger1983$75} {$abc$1984$aiger1983$76} {$abc$1984$aiger1983$77} {$abc$1984$aiger1983$82} {$abc$1984$aiger1983$83} {$abc$1984$aiger1983$84} {$abc$1984$aiger1983$85} {$abc$1984$aiger1983$88} {$abc$1984$aiger1983$89} {$abc$1984$aiger1983$90} {$abc$1984$aiger1983$91} {$abc$1984$aiger1983$92} {$abc$1984$aiger1983$93} {$abc$1984$iopadmap$clk} {$auto$alumacc.cc:485:replace_alu$1385.O} LD6 LD7 LD8 LD9 bottom_inst.I bottom_inst.O bottom_inst.OB bottom_intermediate_inst.I bottom_intermediate_inst.O bottom_intermediate_inst.bottom_intermediate_wire clk counter inter_wire inter_wire_2 led out_a out_b signal_n signal_p
diff --git a/design_introspection-plugin/tests/get_nets/get_nets.tcl b/design_introspection-plugin/tests/get_nets/get_nets.tcl
index c4fe329..2d3083a 100644
--- a/design_introspection-plugin/tests/get_nets/get_nets.tcl
+++ b/design_introspection-plugin/tests/get_nets/get_nets.tcl
@@ -5,7 +5,7 @@
 
 read_verilog get_nets.v
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 
 set fp [open "get_nets.txt" "w"]
diff --git a/design_introspection-plugin/tests/get_pins/get_pins.tcl b/design_introspection-plugin/tests/get_pins/get_pins.tcl
index 144d453..e352df1 100644
--- a/design_introspection-plugin/tests/get_pins/get_pins.tcl
+++ b/design_introspection-plugin/tests/get_pins/get_pins.tcl
@@ -5,7 +5,7 @@
 
 read_verilog get_pins.v
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 
 set fp [open "get_pins.txt" "w"]
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl
index 1ac5903..eca245d 100644
--- a/design_introspection-plugin/tests/get_ports/get_ports.tcl
+++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl
@@ -5,7 +5,7 @@
 
 read_verilog get_ports.v
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 help get_ports
 
 set fp [open "get_ports.txt" "w"]
diff --git a/params-plugin/tests/pll/pll.tcl b/params-plugin/tests/pll/pll.tcl
index cc6e7b3..999abad 100644
--- a/params-plugin/tests/pll/pll.tcl
+++ b/params-plugin/tests/pll/pll.tcl
@@ -38,7 +38,7 @@
 close $fp
 
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check
 
 # Map Xilinx tech library to 7-series VPR tech library.
 read_verilog -lib ./techmaps/cells_sim.v
diff --git a/sdc-plugin/tests/counter/counter.golden.sdc b/sdc-plugin/tests/counter/counter.golden.sdc
index 5be53e3..bf47874 100644
--- a/sdc-plugin/tests/counter/counter.golden.sdc
+++ b/sdc-plugin/tests/counter/counter.golden.sdc
@@ -1,5 +1,5 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1918
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1920
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1801
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1803
 create_clock -period 10 -waveform {0 5} clk_int_1
 create_clock -period 10 -waveform {0 5} ibuf_proxy_out
 create_clock -period 10 -waveform {0 5} middle_inst_1.clk_int
diff --git a/sdc-plugin/tests/counter/counter.golden.txt b/sdc-plugin/tests/counter/counter.golden.txt
index 78277ed..8adab86 100644
--- a/sdc-plugin/tests/counter/counter.golden.txt
+++ b/sdc-plugin/tests/counter/counter.golden.txt
@@ -1 +1 @@
-{$auto$clkbufmap.cc:247:execute$1918} {$auto$clkbufmap.cc:247:execute$1920} clk clk2 clk_int_1 ibuf_proxy_out middle_inst_1.clk_int middle_inst_4.clk
+{$auto$clkbufmap.cc:262:execute$1801} {$auto$clkbufmap.cc:262:execute$1803} clk clk2 clk_int_1 ibuf_proxy_out middle_inst_1.clk_int middle_inst_4.clk
diff --git a/sdc-plugin/tests/counter/counter.tcl b/sdc-plugin/tests/counter/counter.tcl
index b045b3c..e68574b 100644
--- a/sdc-plugin/tests/counter/counter.tcl
+++ b/sdc-plugin/tests/counter/counter.tcl
@@ -8,7 +8,7 @@
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design's timing constraints
 read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/counter2/counter2.golden.sdc b/sdc-plugin/tests/counter2/counter2.golden.sdc
index 33152b3..17624d7 100644
--- a/sdc-plugin/tests/counter2/counter2.golden.sdc
+++ b/sdc-plugin/tests/counter2/counter2.golden.sdc
@@ -1,5 +1,5 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1918
-create_clock -period 10 -waveform {1 6} \$auto\$clkbufmap.cc:247:execute\$1920
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1801
+create_clock -period 10 -waveform {1 6} \$auto\$clkbufmap.cc:262:execute\$1803
 create_clock -period 10 -waveform {0 5} clk_int_1
 create_clock -period 10 -waveform {0 5} ibuf_proxy_out
 create_clock -period 10 -waveform {0 5} middle_inst_1.clk_int
diff --git a/sdc-plugin/tests/counter2/counter2.golden.txt b/sdc-plugin/tests/counter2/counter2.golden.txt
index 78277ed..8adab86 100644
--- a/sdc-plugin/tests/counter2/counter2.golden.txt
+++ b/sdc-plugin/tests/counter2/counter2.golden.txt
@@ -1 +1 @@
-{$auto$clkbufmap.cc:247:execute$1918} {$auto$clkbufmap.cc:247:execute$1920} clk clk2 clk_int_1 ibuf_proxy_out middle_inst_1.clk_int middle_inst_4.clk
+{$auto$clkbufmap.cc:262:execute$1801} {$auto$clkbufmap.cc:262:execute$1803} clk clk2 clk_int_1 ibuf_proxy_out middle_inst_1.clk_int middle_inst_4.clk
diff --git a/sdc-plugin/tests/counter2/counter2.tcl b/sdc-plugin/tests/counter2/counter2.tcl
index 4fcf9be..809b2b8 100644
--- a/sdc-plugin/tests/counter2/counter2.tcl
+++ b/sdc-plugin/tests/counter2/counter2.tcl
@@ -8,7 +8,7 @@
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design's timing constraints
 read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/get_clocks/get_clocks.golden.txt b/sdc-plugin/tests/get_clocks/get_clocks.golden.txt
index 9c70eed..9c94d2d 100644
--- a/sdc-plugin/tests/get_clocks/get_clocks.golden.txt
+++ b/sdc-plugin/tests/get_clocks/get_clocks.golden.txt
@@ -1,5 +1,5 @@
-{$auto$clkbufmap.cc:247:execute$1913} {$auto$clkbufmap.cc:247:execute$1915} clk clk2 clk_int_1 middle_inst_1.clk_int middle_inst_4.clk
-{$auto$clkbufmap.cc:247:execute$1913} {$auto$clkbufmap.cc:247:execute$1915} clk clk2 clk_int_1 middle_inst_1.clk_int middle_inst_4.clk
+{$auto$clkbufmap.cc:262:execute$1800} {$auto$clkbufmap.cc:262:execute$1802} clk clk2 clk_int_1 middle_inst_1.clk_int middle_inst_4.clk
+{$auto$clkbufmap.cc:262:execute$1800} {$auto$clkbufmap.cc:262:execute$1802} clk clk2 clk_int_1 middle_inst_1.clk_int middle_inst_4.clk
 clk2
 clk_int_1
 clk clk2 clk_int_1 middle_inst_1.clk_int middle_inst_4.clk
diff --git a/sdc-plugin/tests/period_check/period_check.tcl b/sdc-plugin/tests/period_check/period_check.tcl
index bc613de..cdfdd25 100644
--- a/sdc-plugin/tests/period_check/period_check.tcl
+++ b/sdc-plugin/tests/period_check/period_check.tcl
@@ -8,7 +8,7 @@
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Propagate the clocks
 propagate_clocks
diff --git a/sdc-plugin/tests/period_format_check/period_format_check.tcl b/sdc-plugin/tests/period_format_check/period_format_check.tcl
index bc613de..cdfdd25 100644
--- a/sdc-plugin/tests/period_format_check/period_format_check.tcl
+++ b/sdc-plugin/tests/period_format_check/period_format_check.tcl
@@ -8,7 +8,7 @@
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Propagate the clocks
 propagate_clocks
diff --git a/sdc-plugin/tests/pll/pll.golden.sdc b/sdc-plugin/tests/pll/pll.golden.sdc
index da025c5..5f1fc75 100644
--- a/sdc-plugin/tests/pll/pll.golden.sdc
+++ b/sdc-plugin/tests/pll/pll.golden.sdc
@@ -1,8 +1,8 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1829
-create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:247:execute\$1831
-create_clock -period 2.5 -waveform {0 1.25} \$auto\$clkbufmap.cc:247:execute\$1833
-create_clock -period 5 -waveform {1.25 3.75} \$auto\$clkbufmap.cc:247:execute\$1835
-create_clock -period 10 -waveform {0 5} \$techmap1716\FDCE_0.C
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1715
+create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:262:execute\$1717
+create_clock -period 2.5 -waveform {0 1.25} \$auto\$clkbufmap.cc:262:execute\$1719
+create_clock -period 5 -waveform {1.25 3.75} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 10 -waveform {0 5} \$techmap1617\FDCE_0.C
 create_clock -period 10 -waveform {2.5 7.5} main_clkout0
 create_clock -period 2.5 -waveform {0 1.25} main_clkout1
 create_clock -period 5 -waveform {1.25 3.75} main_clkout2
diff --git a/sdc-plugin/tests/pll/pll.tcl b/sdc-plugin/tests/pll/pll.tcl
index 5a2e3c4..09973b8 100644
--- a/sdc-plugin/tests/pll/pll.tcl
+++ b/sdc-plugin/tests/pll/pll.tcl
@@ -9,7 +9,7 @@
 hierarchy -check -auto-top
 
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
 read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc
index b97da3e..5e12e7d 100644
--- a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc
+++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc
@@ -1,8 +1,8 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1829
-create_clock -period 9.99999 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1831
-create_clock -period 5 -waveform {-2.5 0} \$auto\$clkbufmap.cc:247:execute\$1833
-create_clock -period 2.5 -waveform {-1.875 -0.624999} \$auto\$clkbufmap.cc:247:execute\$1835
-create_clock -period 10 -waveform {0 5} \$techmap1716\FDCE_0.C
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1715
+create_clock -period 9.99999 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1717
+create_clock -period 5 -waveform {-2.5 0} \$auto\$clkbufmap.cc:262:execute\$1719
+create_clock -period 2.5 -waveform {-1.875 -0.624999} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 10 -waveform {0 5} \$techmap1617\FDCE_0.C
 create_clock -period 9.99999 -waveform {0 5} main_clkout_x1
 create_clock -period 5 -waveform {-2.5 0} main_clkout_x2
 create_clock -period 2.5 -waveform {-1.875 -0.624999} main_clkout_x4
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
index 5a2e3c4..09973b8 100644
--- a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
+++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
@@ -9,7 +9,7 @@
 hierarchy -check -auto-top
 
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
 read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_div/pll_div.golden.sdc b/sdc-plugin/tests/pll_div/pll_div.golden.sdc
index 06031cf..9656011 100644
--- a/sdc-plugin/tests/pll_div/pll_div.golden.sdc
+++ b/sdc-plugin/tests/pll_div/pll_div.golden.sdc
@@ -1,8 +1,8 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1829
-create_clock -period 20 -waveform {5 15} \$auto\$clkbufmap.cc:247:execute\$1831
-create_clock -period 5 -waveform {0 2.5} \$auto\$clkbufmap.cc:247:execute\$1833
-create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:247:execute\$1835
-create_clock -period 10 -waveform {0 5} \$techmap1716\FDCE_0.C
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1715
+create_clock -period 20 -waveform {5 15} \$auto\$clkbufmap.cc:262:execute\$1717
+create_clock -period 5 -waveform {0 2.5} \$auto\$clkbufmap.cc:262:execute\$1719
+create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 10 -waveform {0 5} \$techmap1617\FDCE_0.C
 create_clock -period 20 -waveform {5 15} main_clkout0
 create_clock -period 5 -waveform {0 2.5} main_clkout1
 create_clock -period 10 -waveform {2.5 7.5} main_clkout2
diff --git a/sdc-plugin/tests/pll_div/pll_div.tcl b/sdc-plugin/tests/pll_div/pll_div.tcl
index 5a2e3c4..09973b8 100644
--- a/sdc-plugin/tests/pll_div/pll_div.tcl
+++ b/sdc-plugin/tests/pll_div/pll_div.tcl
@@ -9,7 +9,7 @@
 hierarchy -check -auto-top
 
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
 read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc
index df8301d..f944ef5 100644
--- a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc
+++ b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc
@@ -1,8 +1,8 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1829
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1831
-create_clock -period 5 -waveform {-2.5 0} \$auto\$clkbufmap.cc:247:execute\$1833
-create_clock -period 2.5 -waveform {-1.875 -0.625} \$auto\$clkbufmap.cc:247:execute\$1835
-create_clock -period 10 -waveform {0 5} \$techmap1716\FDCE_0.C
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1715
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1717
+create_clock -period 5 -waveform {-2.5 0} \$auto\$clkbufmap.cc:262:execute\$1719
+create_clock -period 2.5 -waveform {-1.875 -0.625} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 10 -waveform {0 5} \$techmap1617\FDCE_0.C
 create_clock -period 10 -waveform {0 5} main_clkout_x1
 create_clock -period 5 -waveform {-2.5 0} main_clkout_x2
 create_clock -period 2.5 -waveform {-1.875 -0.625} main_clkout_x4
diff --git a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
index 5a2e3c4..09973b8 100644
--- a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
+++ b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
@@ -9,7 +9,7 @@
 hierarchy -check -auto-top
 
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
 read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
index 5e06b2c..223d9ec 100644
--- a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
+++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
@@ -5,7 +5,7 @@
 
 read_verilog set_clock_groups.v
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 set_clock_groups -group clk1 clk2
 set_clock_groups -asynchronous -group clk3 clk4
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.tcl b/sdc-plugin/tests/set_false_path/set_false_path.tcl
index ae14469..dd510f3 100644
--- a/sdc-plugin/tests/set_false_path/set_false_path.tcl
+++ b/sdc-plugin/tests/set_false_path/set_false_path.tcl
@@ -5,7 +5,7 @@
 
 read_verilog $::env(DESIGN_TOP).v
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 # -to inter_wire net
 set_false_path -to inter_wire
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
index f2a5b4f..6b7f23d 100644
--- a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
@@ -5,7 +5,7 @@
 
 read_verilog $::env(DESIGN_TOP).v
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 # -to inter_wire net
 set_max_delay 1 -to inter_wire
diff --git a/sdc-plugin/tests/waveform_check/waveform_check.tcl b/sdc-plugin/tests/waveform_check/waveform_check.tcl
index bc613de..cdfdd25 100644
--- a/sdc-plugin/tests/waveform_check/waveform_check.tcl
+++ b/sdc-plugin/tests/waveform_check/waveform_check.tcl
@@ -8,7 +8,7 @@
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Propagate the clocks
 propagate_clocks
diff --git a/xdc-plugin/tests/counter/counter.tcl b/xdc-plugin/tests/counter/counter.tcl
index be26dde..b6ef30f 100644
--- a/xdc-plugin/tests/counter/counter.tcl
+++ b/xdc-plugin/tests/counter/counter.tcl
@@ -8,7 +8,7 @@
 
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
 read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
index be26dde..b6ef30f 100644
--- a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
+++ b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
@@ -8,7 +8,7 @@
 
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
 read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
index 34d7947..fe1c07c 100644
--- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
+++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
@@ -8,7 +8,7 @@
 read_verilog VexRiscv_Lite.v
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
 read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/package_pins/package_pins.tcl b/xdc-plugin/tests/package_pins/package_pins.tcl
index 2df419a..2e0352e 100644
--- a/xdc-plugin/tests/package_pins/package_pins.tcl
+++ b/xdc-plugin/tests/package_pins/package_pins.tcl
@@ -7,7 +7,7 @@
 read_verilog $::env(DESIGN_TOP).v
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
 read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/port_indexes/port_indexes.tcl b/xdc-plugin/tests/port_indexes/port_indexes.tcl
index 283cce5..e7f8e29 100644
--- a/xdc-plugin/tests/port_indexes/port_indexes.tcl
+++ b/xdc-plugin/tests/port_indexes/port_indexes.tcl
@@ -8,7 +8,7 @@
 
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
-synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 if {[info procs unknown] != ""} {
 	rename unknown ""