)]}'
{
  "commit": "f0bdb131b029841c32a6454218f55b97b665d46b",
  "tree": "1edde825aa6dfb7b8b400d056e4f1a6004641dd8",
  "parents": [
    "fc678f9a26d677f09af2b9e8cb95b3ad66e868e9",
    "91f6d3aca8282bb046dfaaa17cb101878339658f"
  ],
  "author": {
    "name": "Tomasz Gorochowik",
    "email": "tgorochowik@antmicro.com",
    "time": "Thu Apr 14 14:16:47 2022 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Apr 14 14:16:47 2022 +0200"
  },
  "message": "Merge pull request #299 from antmicro/sv-readme\n\nAdd READMEs for the SystemVerilog plugin",
  "tree_diff": []
}