Cleaned DFF simulation models and techmaps, added sync. reset flip-flop models Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v index 90c6db5..ded97d4 100644 --- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v +++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -75,8 +75,6 @@ endmodule - - (* abc9_lut=1, lib_whitebox *) module frac_lut6( input wire [0:5] in, @@ -126,171 +124,36 @@ endmodule + (* abc9_flop, lib_whitebox *) module dff( output reg Q, input wire D, (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) input wire C ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C) - Q <= D; - 1'b1: - always @(negedge C) - Q <= D; - endcase + initial Q <= 1'b0; + + always @(posedge C) + Q <= D; + endmodule (* abc9_flop, lib_whitebox *) -module dffr( +module dffn( output reg Q, input wire D, - input wire R, (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) input wire C ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or posedge R) - if (R) - Q <= 1'b0; - else - Q <= D; - 1'b1: - always @(negedge C or posedge R) - if (R) - Q <= 1'b0; - else - Q <= D; - endcase + initial Q <= 1'b0; + + always @(negedge C) + Q <= D; + endmodule (* abc9_flop, lib_whitebox *) -module dffre( - output reg Q, - input wire D, - input wire R, - input wire E, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input wire C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or posedge R) - if (R) - Q <= 1'b0; - else if(E) - Q <= D; - 1'b1: - always @(negedge C or posedge R) - if (R) - Q <= 1'b0; - else if(E) - Q <= D; - endcase -endmodule - -module dffs( - output reg Q, - input wire D, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input wire C, - input wire S -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or negedge S) - if (S) - Q <= 1'b1; - else - Q <= D; - 1'b1: - always @(negedge C or negedge S) - if (S) - Q <= 1'b1; - else - Q <= D; - endcase -endmodule - -module dffse( - output reg Q, - input wire D, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input wire C, - input wire S, - input wire E -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or negedge S) - if (S) - Q <= 1'b1; - else if(E) - Q <= D; - 1'b1: - always @(negedge C or negedge S) - if (S) - Q <= 1'b1; - else if(E) - Q <= D; - endcase -endmodule - -module dffsr( - output reg Q, - input wire D, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input wire C, - input wire R, - input wire S -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or negedge S or negedge R) - if (S) - Q <= 1'b1; - else if (R) - Q <= 1'b0; - else - Q <= D; - 1'b1: - always @(negedge C or negedge S or negedge R) - if (S) - Q <= 1'b1; - else if (R) - Q <= 1'b0; - else - Q <= D; - endcase -endmodule - module dffsre( output reg Q, input wire D, @@ -300,19 +163,19 @@ input wire R, input wire S ); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; + initial Q <= 1'b0; - always @(posedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - + always @(posedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + endmodule +(* abc9_flop, lib_whitebox *) module dffnsre( output reg Q, input wire D, @@ -322,17 +185,86 @@ input wire R, input wire S ); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; + initial Q <= 1'b0; - always @(negedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - + always @(negedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(posedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffnsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(negedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + +endmodule + +(* abc9_flop, lib_whitebox *) +module latch ( + output reg Q, + input wire D, + input wire G +); + initial Q <= 1'b0; + + always @(G) + if (G) Q <= D; + +endmodule + +(* abc9_flop, lib_whitebox *) +module latchn ( + output reg Q, + input wire D, + input wire G +); + initial Q <= 1'b0; + + always @(G) + if (!G) Q <= D; + endmodule (* abc9_flop, lib_whitebox *) @@ -344,17 +276,18 @@ input wire G, input wire E ); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; + initial Q <= 1'b0; + always @* begin - if (!R) + if (!R) Q <= 1'b0; - else if (!S) + else if (!S) Q <= 1'b1; - else if (E && G) + else if (E && G) Q <= D; end + endmodule (* abc9_flop, lib_whitebox *) @@ -366,31 +299,20 @@ input wire G, input wire E ); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; + initial Q <= 1'b0; + always @* begin - if (!R) + if (!R) Q <= 1'b0; - else if (!S) + else if (!S) Q <= 1'b1; - else if (E && !G) + else if (E && !G) Q <= D; end + endmodule -(* abc9_flop, lib_whitebox *) -module scff( - output reg Q, - input wire D, - input wire clk -); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - - always @(posedge clk) - Q <= D; -endmodule module TDP_BRAM18 ( (* clkbuf_sink *) @@ -1255,10 +1177,10 @@ assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0); assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0); assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 - }; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 + }; end 2: begin @@ -1266,10 +1188,10 @@ assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 14'd0); assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 1) : (F1EN ? (F1ADDR_TOTAL << 1) : 14'd0); assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 1) : (H1EN ? (H1ADDR_TOTAL << 1) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 - }; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 + }; end 4: begin @@ -1277,10 +1199,10 @@ assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 14'd0); assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 2) : (F1EN ? (F1ADDR_TOTAL << 2) : 14'd0); assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 2) : (H1EN ? (H1ADDR_TOTAL << 2) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 - }; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 + }; end 8, 9: begin @@ -1288,10 +1210,10 @@ assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 14'd0); assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 3) : (F1EN ? (F1ADDR_TOTAL << 3) : 14'd0); assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 3) : (H1EN ? (H1ADDR_TOTAL << 3) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 - }; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 + }; end 16, 18: begin @@ -1299,10 +1221,10 @@ assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 14'd0); assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 4) : (F1EN ? (F1ADDR_TOTAL << 4) : 14'd0); assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 4) : (H1EN ? (H1ADDR_TOTAL << 4) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 - }; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 + }; end default: begin @@ -1310,10 +1232,10 @@ assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0); assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0); assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 - }; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 + }; end endcase @@ -1390,15 +1312,15 @@ endmodule module BRAM2x18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN); - parameter CFG_ABITS = 11; - parameter CFG_DBITS = 18; - parameter CFG_ENABLE_B = 4; - parameter CFG_ENABLE_D = 4; + parameter CFG_ABITS = 11; + parameter CFG_DBITS = 18; + parameter CFG_ENABLE_B = 4; + parameter CFG_ENABLE_D = 4; - parameter CLKPOL2 = 1; - parameter CLKPOL3 = 1; - parameter [18431:0] INIT0 = 18432'bx; - parameter [18431:0] INIT1 = 18432'bx; + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT0 = 18432'bx; + parameter [18431:0] INIT1 = 18432'bx; localparam MODE_36 = 3'b011; // 36- or 32-bit localparam MODE_18 = 3'b010; // 18- or 16-bit @@ -1407,209 +1329,209 @@ localparam MODE_2 = 3'b110; // 2-bit localparam MODE_1 = 3'b101; // 1-bit - input CLK1; - input CLK2; + input CLK1; + input CLK2; - input [CFG_ABITS-1:0] A1ADDR; - output [CFG_DBITS-1:0] A1DATA; - input A1EN; + input [CFG_ABITS-1:0] A1ADDR; + output [CFG_DBITS-1:0] A1DATA; + input A1EN; - input [CFG_ABITS-1:0] B1ADDR; - input [CFG_DBITS-1:0] B1DATA; - input [CFG_ENABLE_B-1:0] B1EN; + input [CFG_ABITS-1:0] B1ADDR; + input [CFG_DBITS-1:0] B1DATA; + input [CFG_ENABLE_B-1:0] B1EN; - input [CFG_ABITS-1:0] C1ADDR; - output [CFG_DBITS-1:0] C1DATA; - input C1EN; + input [CFG_ABITS-1:0] C1ADDR; + output [CFG_DBITS-1:0] C1DATA; + input C1EN; - input [CFG_ABITS-1:0] D1ADDR; - input [CFG_DBITS-1:0] D1DATA; - input [CFG_ENABLE_D-1:0] D1EN; + input [CFG_ABITS-1:0] D1ADDR; + input [CFG_DBITS-1:0] D1DATA; + input [CFG_ENABLE_D-1:0] D1EN; - wire FLUSH1; - wire FLUSH2; + wire FLUSH1; + wire FLUSH2; - wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR}; - wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR}; - wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR}; - wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR}; + wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR}; + wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR}; + wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR}; + wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR}; - wire [17:CFG_DBITS] A1_RDATA_CMPL; - wire [17:CFG_DBITS] C1_RDATA_CMPL; + wire [17:CFG_DBITS] A1_RDATA_CMPL; + wire [17:CFG_DBITS] C1_RDATA_CMPL; - wire [17:CFG_DBITS] B1_WDATA_CMPL; - wire [17:CFG_DBITS] D1_WDATA_CMPL; + wire [17:CFG_DBITS] B1_WDATA_CMPL; + wire [17:CFG_DBITS] D1_WDATA_CMPL; - wire [13:0] PORT_A1_ADDR; - wire [13:0] PORT_A2_ADDR; - wire [13:0] PORT_B1_ADDR; - wire [13:0] PORT_B2_ADDR; + wire [13:0] PORT_A1_ADDR; + wire [13:0] PORT_A2_ADDR; + wire [13:0] PORT_B1_ADDR; + wire [13:0] PORT_B2_ADDR; - case (CFG_DBITS) - 1: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL; - assign PORT_B1_ADDR = B1ADDR_TOTAL; - assign PORT_A2_ADDR = C1ADDR_TOTAL; - assign PORT_B2_ADDR = D1ADDR_TOTAL; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 - }; - end + case (CFG_DBITS) + 1: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL; + assign PORT_B1_ADDR = B1ADDR_TOTAL; + assign PORT_A2_ADDR = C1ADDR_TOTAL; + assign PORT_B2_ADDR = D1ADDR_TOTAL; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 + }; + end - 2: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 1; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 1; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 1; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 1; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 - }; - end + 2: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 1; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 1; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 1; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 1; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 + }; + end - 4: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 2; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 2; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 2; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 2; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 - }; - end + 4: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 2; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 2; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 2; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 2; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 + }; + end - 8, 9: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 3; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 3; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 3; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 3; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 - }; - end + 8, 9: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 3; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 3; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 3; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 3; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 + }; + end - 16, 18: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 4; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 4; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 4; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 4; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 - }; - end + 16, 18: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 4; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 4; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 4; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 4; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 + }; + end - default: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL; - assign PORT_B1_ADDR = B1ADDR_TOTAL; - assign PORT_A2_ADDR = D1ADDR_TOTAL; - assign PORT_B2_ADDR = C1ADDR_TOTAL; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 - }; - end - endcase + default: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL; + assign PORT_B1_ADDR = B1ADDR_TOTAL; + assign PORT_A2_ADDR = D1ADDR_TOTAL; + assign PORT_B2_ADDR = C1ADDR_TOTAL; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 + }; + end + endcase - assign FLUSH1 = 1'b0; - assign FLUSH2 = 1'b0; + assign FLUSH1 = 1'b0; + assign FLUSH2 = 1'b0; - wire [17:0] PORT_A1_RDATA; - wire [17:0] PORT_B1_RDATA; - wire [17:0] PORT_A2_RDATA; - wire [17:0] PORT_B2_RDATA; + wire [17:0] PORT_A1_RDATA; + wire [17:0] PORT_B1_RDATA; + wire [17:0] PORT_A2_RDATA; + wire [17:0] PORT_B2_RDATA; - wire [17:0] PORT_A1_WDATA; - wire [17:0] PORT_B1_WDATA; - wire [17:0] PORT_A2_WDATA; - wire [17:0] PORT_B2_WDATA; + wire [17:0] PORT_A1_WDATA; + wire [17:0] PORT_B1_WDATA; + wire [17:0] PORT_A2_WDATA; + wire [17:0] PORT_B2_WDATA; - // Assign read/write data - handle special case for 9bit mode - // parity bit for 9bit mode is placed in R/W port on bit #16 - case (CFG_DBITS) - 9: begin - assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]}; - assign C1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]}; - assign PORT_A1_WDATA = {18{1'b0}}; - assign PORT_B1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]}; - assign PORT_A2_WDATA = {18{1'b0}}; - assign PORT_B2_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]}; - end - default: begin - assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0]; - assign C1DATA = PORT_A2_RDATA[CFG_DBITS-1:0]; - assign PORT_A1_WDATA = {18{1'b1}}; - assign PORT_B1_WDATA = {B1_WDATA_CMPL, B1DATA}; - assign PORT_A2_WDATA = {18{1'b1}}; - assign PORT_B2_WDATA = {D1_WDATA_CMPL, D1DATA}; + // Assign read/write data - handle special case for 9bit mode + // parity bit for 9bit mode is placed in R/W port on bit #16 + case (CFG_DBITS) + 9: begin + assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]}; + assign C1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]}; + assign PORT_A1_WDATA = {18{1'b0}}; + assign PORT_B1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]}; + assign PORT_A2_WDATA = {18{1'b0}}; + assign PORT_B2_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]}; + end + default: begin + assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0]; + assign C1DATA = PORT_A2_RDATA[CFG_DBITS-1:0]; + assign PORT_A1_WDATA = {18{1'b1}}; + assign PORT_B1_WDATA = {B1_WDATA_CMPL, B1DATA}; + assign PORT_A2_WDATA = {18{1'b1}}; + assign PORT_B2_WDATA = {D1_WDATA_CMPL, D1DATA}; - end - endcase + end + endcase - wire PORT_A1_CLK = CLK1; - wire PORT_A2_CLK = CLK2; - wire PORT_B1_CLK = CLK1; - wire PORT_B2_CLK = CLK2; + wire PORT_A1_CLK = CLK1; + wire PORT_A2_CLK = CLK2; + wire PORT_B1_CLK = CLK1; + wire PORT_B2_CLK = CLK2; - wire PORT_A1_REN = A1EN; - wire PORT_A1_WEN = 1'b0; - wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {PORT_A1_WEN,PORT_A1_WEN}; + wire PORT_A1_REN = A1EN; + wire PORT_A1_WEN = 1'b0; + wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {PORT_A1_WEN,PORT_A1_WEN}; - wire PORT_A2_REN = C1EN; - wire PORT_A2_WEN = 1'b0; - wire [CFG_ENABLE_D-1:0] PORT_A2_BE = {PORT_A2_WEN,PORT_A2_WEN}; + wire PORT_A2_REN = C1EN; + wire PORT_A2_WEN = 1'b0; + wire [CFG_ENABLE_D-1:0] PORT_A2_BE = {PORT_A2_WEN,PORT_A2_WEN}; - wire PORT_B1_REN = 1'b0; - wire PORT_B1_WEN = B1EN[0]; - wire [CFG_ENABLE_B-1:0] PORT_B1_BE = {B1EN[1],B1EN[0]}; + wire PORT_B1_REN = 1'b0; + wire PORT_B1_WEN = B1EN[0]; + wire [CFG_ENABLE_B-1:0] PORT_B1_BE = {B1EN[1],B1EN[0]}; - wire PORT_B2_REN = 1'b0; - wire PORT_B2_WEN = D1EN[0]; - wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]}; + wire PORT_B2_REN = 1'b0; + wire PORT_B2_WEN = D1EN[0]; + wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]}; - TDP36K bram_2x18k ( - .WDATA_A1_i(PORT_A1_WDATA), - .RDATA_A1_o(PORT_A1_RDATA), - .ADDR_A1_i(PORT_A1_ADDR), - .CLK_A1_i(PORT_A1_CLK), - .REN_A1_i(PORT_A1_REN), - .WEN_A1_i(PORT_A1_WEN), - .BE_A1_i(PORT_A1_BE), + TDP36K bram_2x18k ( + .WDATA_A1_i(PORT_A1_WDATA), + .RDATA_A1_o(PORT_A1_RDATA), + .ADDR_A1_i(PORT_A1_ADDR), + .CLK_A1_i(PORT_A1_CLK), + .REN_A1_i(PORT_A1_REN), + .WEN_A1_i(PORT_A1_WEN), + .BE_A1_i(PORT_A1_BE), - .WDATA_A2_i(PORT_A2_WDATA), - .RDATA_A2_o(PORT_A2_RDATA), - .ADDR_A2_i(PORT_A2_ADDR), - .CLK_A2_i(PORT_A2_CLK), - .REN_A2_i(PORT_A2_REN), - .WEN_A2_i(PORT_A2_WEN), - .BE_A2_i(PORT_A2_BE), + .WDATA_A2_i(PORT_A2_WDATA), + .RDATA_A2_o(PORT_A2_RDATA), + .ADDR_A2_i(PORT_A2_ADDR), + .CLK_A2_i(PORT_A2_CLK), + .REN_A2_i(PORT_A2_REN), + .WEN_A2_i(PORT_A2_WEN), + .BE_A2_i(PORT_A2_BE), - .WDATA_B1_i(PORT_B1_WDATA), - .RDATA_B1_o(PORT_B1_RDATA), - .ADDR_B1_i(PORT_B1_ADDR), - .CLK_B1_i(PORT_B1_CLK), - .REN_B1_i(PORT_B1_REN), - .WEN_B1_i(PORT_B1_WEN), - .BE_B1_i(PORT_B1_BE), + .WDATA_B1_i(PORT_B1_WDATA), + .RDATA_B1_o(PORT_B1_RDATA), + .ADDR_B1_i(PORT_B1_ADDR), + .CLK_B1_i(PORT_B1_CLK), + .REN_B1_i(PORT_B1_REN), + .WEN_B1_i(PORT_B1_WEN), + .BE_B1_i(PORT_B1_BE), - .WDATA_B2_i(PORT_B2_WDATA), - .RDATA_B2_o(PORT_B2_RDATA), - .ADDR_B2_i(PORT_B2_ADDR), - .CLK_B2_i(PORT_B2_CLK), - .REN_B2_i(PORT_B2_REN), - .WEN_B2_i(PORT_B2_WEN), - .BE_B2_i(PORT_B2_BE), + .WDATA_B2_i(PORT_B2_WDATA), + .RDATA_B2_o(PORT_B2_RDATA), + .ADDR_B2_i(PORT_B2_ADDR), + .CLK_B2_i(PORT_B2_CLK), + .REN_B2_i(PORT_B2_REN), + .WEN_B2_i(PORT_B2_WEN), + .BE_B2_i(PORT_B2_BE), - .FLUSH1_i(FLUSH1), - .FLUSH2_i(FLUSH2) - ); + .FLUSH1_i(FLUSH1), + .FLUSH2_i(FLUSH2) + ); endmodule (* blackbox *) @@ -1812,7 +1734,7 @@ .b(b), .z(z), - .reset(reset), + .reset(reset), .f_mode(f_mode), @@ -1821,7 +1743,7 @@ .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), - .output_select(3'b0), // unregistered output: a * b (0) + .output_select(3'b0), // unregistered output: a * b (0) .register_inputs(1'b0) // unregistered inputs ); endmodule @@ -1866,9 +1788,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(3'b0), // unregistered output: a * b (0) + .output_select(3'b0), // unregistered output: a * b (0) .register_inputs(1'b1) // registered inputs ); endmodule @@ -1912,9 +1834,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(3'b100), // registered output: a * b (4) + .output_select(3'b100), // registered output: a * b (4) .register_inputs(1'b0) // unregistered inputs ); endmodule @@ -1958,9 +1880,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(3'b100), // registered output: a * b (4) + .output_select(3'b100), // registered output: a * b (4) .register_inputs(1'b1) // registered inputs ); endmodule @@ -2010,9 +1932,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(output_select), // unregistered output: ACCin (2, 3) + .output_select(output_select), // unregistered output: ACCin (2, 3) .subtract(subtract), .register_inputs(1'b0) // unregistered inputs ); @@ -2062,9 +1984,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(output_select), // unregistered output: ACCin (2, 3) + .output_select(output_select), // unregistered output: ACCin (2, 3) .subtract(subtract), .register_inputs(1'b1) // registered inputs ); @@ -2114,9 +2036,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(output_select), // registered output: ACCin (6, 7) + .output_select(output_select), // registered output: ACCin (6, 7) .subtract(subtract), .register_inputs(1'b0) // unregistered inputs ); @@ -2166,9 +2088,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(output_select), // registered output: ACCin (6, 7) + .output_select(output_select), // registered output: ACCin (6, 7) .subtract(subtract), .register_inputs(1'b1) // registered inputs ); @@ -2212,8 +2134,8 @@ .f_mode(f_mode), - .feedback(feedback), - .load_acc(load_acc), + .feedback(feedback), + .load_acc(load_acc), .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), @@ -2221,7 +2143,7 @@ .clk(clk), .reset(reset), - .output_select(1'b1), // unregistered output: ACCout (1) + .output_select(1'b1), // unregistered output: ACCout (1) .subtract(subtract), .register_inputs(1'b0) // unregistered inputs ); @@ -2271,9 +2193,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(1'b1), // unregistered output: ACCout (1) + .output_select(1'b1), // unregistered output: ACCout (1) .subtract(subtract), .register_inputs(1'b1) // registered inputs ); @@ -2317,15 +2239,15 @@ .f_mode(f_mode), .feedback(feedback), - .load_acc(load_acc), + .load_acc(load_acc), .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(3'b101), // registered output: ACCout (5) + .output_select(3'b101), // registered output: ACCout (5) .subtract(subtract), .register_inputs(1'b0) // unregistered inputs ); @@ -2375,9 +2297,9 @@ .unsigned_b(unsigned_b), .clk(clk), - .reset(reset), + .reset(reset), - .output_select(3'b101), // registered output: ACCout (5) + .output_select(3'b101), // registered output: ACCout (5) .subtract(subtract), .register_inputs(1'b1) // registered inputs );
diff --git a/ql-qlf-plugin/qlf_k6n10f/ffs_map.v b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v index 273f28e..fe665fa 100644 --- a/ql-qlf-plugin/qlf_k6n10f/ffs_map.v +++ b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v
@@ -14,566 +14,94 @@ // // SPDX-License-Identifier: Apache-2.0 -// Basic DFF - +// DFF, no set/reset, no enable module \$_DFF_P_ (D, C, Q); - input D; - input C; + input D; + input C; output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(1'b1)); + dff _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); endmodule -// Async reset -module \$_DFF_PP0_ (D, C, R, Q); - input D; - input C; - input R; +module \$_DFF_N_ (D, C, Q); + input D; + input C; output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(1'b1)); + dffn _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); endmodule -// Async reset -module \$_DFF_PN0_ (D, C, R, Q); - input D; - input C; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(1'b1)); -endmodule - -// Async set -module \$_DFF_PP1_ (D, C, R, Q); - input D; - input C; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(!R)); -endmodule - -// Async set -module \$_DFF_PN1_ (D, C, R, Q); - input D; - input C; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(R)); -endmodule - -module \$_DFFE_PP_ (D, C, E, Q); - input D; - input C; - input E; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(1'b1)); -endmodule - -module \$_DFFE_PN_ (D, C, E, Q); - input D; - input C; - input E; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(1'b1)); -endmodule - -// Async reset, enable -module \$_DFFE_PP0P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(1'b1)); -endmodule - -module \$_DFFE_PP0N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(1'b1)); -endmodule - -module \$_DFFE_PN0P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); -endmodule - -module \$_DFFE_PN0N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(1'b1)); -endmodule -// Async set, enable - -module \$_DFFE_PP1P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(!R)); -endmodule - -module \$_DFFE_PP1N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(!R)); -endmodule - -module \$_DFFE_PN1P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); -endmodule - -module \$_DFFE_PN1N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(R)); -endmodule - -// Async set & reset - -module \$_DFFSR_PPP_ (D, C, R, S, Q); - input D; - input C; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(!S)); -endmodule - -module \$_DFFSR_PNP_ (D, Q, C, R, S); - input D; - input C; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(S)); -endmodule - -module \$_DFFSR_PNN_ (D, Q, C, R, S); - input D; - input C; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(S)); -endmodule - -module \$_DFFSR_PPN_ (D, Q, C, R, S); - input D; - input C; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(!S)); -endmodule - -module \$_DFFSR_NPP_ (D, Q, C, R, S); - input D; - input C; - input R; - input S; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(!S)); -endmodule - -module \$_DFFSR_NNP_ (D, Q, C, R, S); - input D; - input C; - input R; - input S; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(S)); -endmodule - -module \$_DFFSR_NNN_ (D, Q, C, R, S); - input D; - input C; - input R; - input S; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(S)); -endmodule - -module \$_DFFSR_NPN_ (D, Q, C, R, S); - input D; - input C; - input R; - input S; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(!S)); -endmodule - -// Async set, reset & enable - -module \$_DFFSRE_PPPP_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(!S)); -endmodule - -module \$_DFFSRE_PNPP_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(S)); -endmodule - -module \$_DFFSRE_PPNP_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(!S)); -endmodule - -module \$_DFFSRE_PNNP_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; +// DFF, asynchronous set/reset, enable +module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; output Q; dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule -module \$_DFFSRE_PPPN_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(!S)); -endmodule - -module \$_DFFSRE_PNPN_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(S)); -endmodule - -module \$_DFFSRE_PPNN_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(!S)); -endmodule - -module \$_DFFSRE_PNNN_ (D, Q, C, E, R, S); - input D; - input C; - input E; - input R; - input S; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(S)); -endmodule - -// Latch with async set and reset -module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); - latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); -endmodule - -module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); - latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); -endmodule - -// The following techmap operation are not performed right now -// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10 -// but in case we implement clock inversion in the future, the support is ready for it. - -module \$_DFF_N_ (D, C, Q); - input D; - input C; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(1'b1)); -endmodule - -module \$_DFF_NP0_ (D, C, R, Q); - input D; - input C; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(1'b1)); -endmodule - -module \$_DFF_NN0_ (D, C, R, Q); - input D; - input C; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(1'b1)); -endmodule - -module \$_DFF_NP1_ (D, C, R, Q); - input D; - input C; - input R; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(!R)); -endmodule - -module \$_DFF_NN1_ (D, C, R, Q); - input D; - input C; - input R; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(R)); -endmodule - -module \$_DFFE_NP_ (D, C, E, Q); - input D; - input C; - input E; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(1'b1)); -endmodule - -module \$_DFFE_NN_ (D, C, E, Q); - input D; - input C; - input E; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(1'b1)); -endmodule - -module \$_DFFE_NP0P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(1'b1)); -endmodule - -module \$_DFFE_NP0N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(1'b1)); -endmodule - -module \$_DFFE_NN0P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); -endmodule - -module \$_DFFE_NN0N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(1'b1)); -endmodule - -module \$_DFFE_NP1P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(!R)); -endmodule - -module \$_DFFE_NP1N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(!R)); -endmodule - -module \$_DFFE_NN1P_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); -endmodule - -module \$_DFFE_NN1N_ (D, C, E, R, Q); - input D; - input C; - input E; - input R; - output Q; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(R)); -endmodule - -module \$_DFFSRE_NPPP_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(!S)); -endmodule - -module \$_DFFSRE_NNPP_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(S)); -endmodule - -module \$_DFFSRE_NPNP_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(!S)); -endmodule - -module \$_DFFSRE_NNNP_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; +module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; output Q; dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule - -module \$_DFFSRE_NPPN_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; +// DFF, synchronous set or reset, enable +module \$_SDFFE_PN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(!S)); + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule -module \$_DFFSRE_NNPN_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; +module \$_SDFFE_PN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(S)); + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule -module \$_DFFSRE_NPNN_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; +module \$_SDFFE_NN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(!S)); + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule -module \$_DFFSRE_NNNN_ (D, C, E, R, S, Q); - input D; - input C; - input E; - input R; - input S; +module \$_SDFFE_NN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(S)); + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule -module \$__SHREG_DFF_P_ (D, Q, C); - input D; - input C; - output Q; +// Latch, no set/reset, no enable +module \$_DLATCH_P_ (input E, D, output Q); + latch _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E)); +endmodule - parameter DEPTH = 2; - reg [DEPTH-2:0] q; - genvar i; - generate for (i = 0; i < DEPTH; i = i + 1) begin: slice +module \$_DLATCH_N_ (input E, D, output Q); + latchn _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E)); +endmodule +// Latch with async set and reset and enable +module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); +endmodule - // First in chain - generate if (i == 0) begin - sh_dff #() shreg_beg ( - .Q(q[i]), - .D(D), - .C(C) - ); - end endgenerate - // Middle in chain - generate if (i > 0 && i != DEPTH-1) begin - sh_dff #() shreg_mid ( - .Q(q[i]), - .D(q[i-1]), - .C(C) - ); - end endgenerate - // Last in chain - generate if (i == DEPTH-1) begin - sh_dff #() shreg_end ( - .Q(Q), - .D(q[i-1]), - .C(C) - ); - end endgenerate - end: slice - endgenerate - +module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); endmodule