systemverilog-plugin: convert memory when accessing slice

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index f0dbade..236fe7c 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -428,8 +428,26 @@
             }
         }
         if (node->type == AST::AST_IDENTIFIER && memories.count(node->str)) {
-            if (!memories[node->str]->attributes.count(UhdmAst::force_convert()) && node->children.size() == 0) {
-                add_force_convert_attribute(memories[node->str]);
+            if (!memories[node->str]->attributes.count(UhdmAst::force_convert())) {
+                bool force_convert = false;
+                // convert memory to list of registers
+                // in case of access to whole memory
+                // or slice of memory
+                // e.g.
+                // logic [3:0] mem [8:0];
+                // always_ff @ (posedge clk) begin
+                //   mem <= '{default:0};
+                //   mem[7:1] <= mem[6:0];
+                // end
+                if (node->children.size() == 0) {
+                    force_convert = true;
+                }
+                if (node->children.size() == 1 && node->children[0]->children.size() != 1) {
+                    force_convert = true;
+                }
+                if (force_convert) {
+                    add_force_convert_attribute(memories[node->str]);
+                }
             }
         }
     });