)]}'
{
  "commit": "f4ce6487b4fd638fef393905673b7df224916f74",
  "tree": "2889d3b4c063618ad75f95626e7f9e2bee35f430",
  "parents": [
    "ac62c6351f5a5885c10aae41c2a6f4d3a363ba5d"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Fri Feb 17 15:08:23 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Fri Feb 17 15:13:11 2023 +0100"
  },
  "message": "systemverilog-plugin: convert memory when accessing slice\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f0dbade5aab96a7ee1da86228fb8ca546d1005b1",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "236fe7cc9039b2db68e007e7dbb2472500c6248e",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}