)]}'
{
  "commit": "f53aff89c65d03bbbb552808a5f128f9d9bbe703",
  "tree": "254b406838c22d0c406673c66b2da497b69f634b",
  "parents": [
    "e0a923cc0bf6b2149994857ba47dc71c5791f227"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Thu Mar 09 17:31:44 2023 +0100"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Wed Mar 22 17:22:03 2023 +0100"
  },
  "message": "use reduceExpr to evaluate logic typespecs\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2dc7f0c724b25d90aeac69592db1926d7b3d85ad",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "ca8f32d5dc4fe8d7089db6b779c903ce618ee996",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}