diff --git a/design_introspection-plugin/get_ports.cc b/design_introspection-plugin/get_ports.cc
index 241a00a..1eaad8b 100644
--- a/design_introspection-plugin/get_ports.cc
+++ b/design_introspection-plugin/get_ports.cc
@@ -27,37 +27,36 @@
 	Tcl_ListObjAppendElement(yosys_get_tcl_interp(), tcl_list, value_obj);
     }
 }
-/* void GetPorts::execute(std::vector<std::string> args, RTLIL::Design* design)
- * { */
-/*     if (args.size() < 2) { */
-/* 	log_cmd_error("No port specified.\n"); */
-/*     } */
-/*     RTLIL::Module* top_module = design->top_module(); */
-/*     if (top_module == nullptr) { */
-/* 	log_cmd_error("No top module detected\n"); */
-/*     } */
-/*     // TODO handle more than one port */
-/*     std::string port_name = args.at(1); */
-/*     std::string port_str(port_name.size(), '\0'); */
-/*     int bit(0); */
-/*     if (!sscanf(port_name.c_str(), "%[^[][%d]", &port_str[0], &bit)) { */
-/* 	log_error("Couldn't find port %s\n", port_name.c_str()); */
-/*     } */
 
-/*     port_str.resize(strlen(port_str.c_str())); */
-/*     RTLIL::IdString port_id(RTLIL::escape_id(port_str)); */
-/*     Tcl_Interp* interp = yosys_get_tcl_interp(); */
-/*     if (auto wire = top_module->wire(port_id)) { */
-/* 	if (wire->port_input || wire->port_output) { */
-/* 	    if (bit >= wire->start_offset && */
-/* 	        bit < wire->start_offset + wire->width) { */
-/* 		Tcl_Obj* tcl_string = Tcl_NewStringObj(port_name.c_str(), -1);
- */
-/* 		Tcl_SetObjResult(interp, tcl_string); */
-/* 		log("Found port %s\n", port_name.c_str()); */
-/* 		return; */
-/* 	    } */
-/* 	} */
-/*     } */
-/*     log_error("Couldn't find port %s\n", port_name.c_str()); */
-/* } */
+void GetPorts::execute(std::vector<std::string> args, RTLIL::Design* design) {
+    if (args.size() < 2) {
+	log_cmd_error("No port specified.\n");
+    }
+    RTLIL::Module* top_module = design->top_module();
+    if (top_module == nullptr) {
+	log_cmd_error("No top module detected\n");
+    }
+    // TODO handle more than one port
+    std::string port_name = args.at(1);
+    std::string port_str(port_name.size(), '\0');
+    int bit(0);
+    if (!sscanf(port_name.c_str(), "%[^[][%d]", &port_str[0], &bit)) {
+	log_error("Couldn't find port %s\n", port_name.c_str());
+    }
+
+    port_str.resize(strlen(port_str.c_str()));
+    RTLIL::IdString port_id(RTLIL::escape_id(port_str));
+    Tcl_Interp* interp = yosys_get_tcl_interp();
+    if (auto wire = top_module->wire(port_id)) {
+	if (wire->port_input || wire->port_output) {
+	    if (bit >= wire->start_offset &&
+	        bit < wire->start_offset + wire->width) {
+		Tcl_Obj* tcl_string = Tcl_NewStringObj(port_name.c_str(), -1);
+		Tcl_SetObjResult(interp, tcl_string);
+		log("Found port %s\n", port_name.c_str());
+		return;
+	    }
+	}
+    }
+    log_error("Couldn't find port %s\n", port_name.c_str());
+}
diff --git a/design_introspection-plugin/get_ports.h b/design_introspection-plugin/get_ports.h
index eb8c099..f00dd5f 100644
--- a/design_introspection-plugin/get_ports.h
+++ b/design_introspection-plugin/get_ports.h
@@ -12,6 +12,7 @@
     std::string SelectionType() override;
     void ExtractSelection(Tcl_Obj* tcl_list, RTLIL::Module* module,
                           Filters& filters, bool is_quiet) override;
+    void execute(std::vector<std::string> args, RTLIL::Design* design) override;
 };
 
 #endif  // GET_PORTS_H_
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.golden.txt b/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
index 16e7e98..d87ba55 100644
--- a/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
+++ b/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
@@ -1,10 +1,6 @@
-signal_* ports quiet
-signal_n signal_p
-signal_* ports
-signal_n signal_p
-led ports with filter expression
-led
-Filtered ports
+signal_p port
+signal_p
+clk port
 clk
-All ports
-clk led out_a out_b signal_n signal_p
+led[0] port
+led[0]
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl
index b71fd65..1ac5903 100644
--- a/design_introspection-plugin/tests/get_ports/get_ports.tcl
+++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl
@@ -10,24 +10,36 @@
 
 set fp [open "get_ports.txt" "w"]
 
-puts "\nsignal_* ports quiet"
-puts $fp "signal_* ports quiet"
-puts $fp [get_ports -quiet signal_*]
+puts "\nsignal_p port"
+puts $fp "signal_p port"
+puts $fp [get_ports signal_p]
 
-puts "\nsignal_* ports"
-puts $fp "signal_* ports"
-puts $fp [get_ports signal_*]
+puts "\nclk port"
+puts $fp "clk port"
+puts $fp [get_ports clk]
 
-puts "\nled ports with filter expression"
-puts $fp "led ports with filter expression"
-puts $fp [get_ports -filter {mr_ff != true} led]
+puts {\nled[0] port}
+puts $fp {led[0] port}
+puts $fp [get_ports {led[0]}]
 
-puts "\nFiltered ports"
-puts $fp "Filtered ports"
-puts $fp [get_ports -filter {mr_ff == true || async_reg == true && dont_touch == true} ]
-
-puts "\nAll ports"
-puts $fp "All ports"
-puts $fp [get_ports]
+#puts "\nsignal_* ports quiet"
+#puts $fp "signal_* ports quiet"
+#puts $fp [get_ports -quiet signal_*]
+#
+#puts "\nsignal_* ports"
+#puts $fp "signal_* ports"
+#puts $fp [get_ports signal_*]
+#
+#puts "\nled ports with filter expression"
+#puts $fp "led ports with filter expression"
+#puts $fp [get_ports -filter {mr_ff != true} led]
+#
+#puts "\nFiltered ports"
+#puts $fp "Filtered ports"
+#puts $fp [get_ports -filter {mr_ff == true || async_reg == true && dont_touch == true} ]
+#
+#puts "\nAll ports"
+#puts $fp "All ports"
+#puts $fp [get_ports]
 
 close $fp