)]}'
{
  "commit": "f858e49a160a8e36b061bb79926d8a4b5c5fc8ca",
  "tree": "cb09a2984deb92a8389844b1aa8c8897fb93b064",
  "parents": [
    "ec8cfe7871d73c3202ae5b7bc425c91021889e57"
  ],
  "author": {
    "name": "Tomasz Michalak",
    "email": "tmichalak@antmicro.com",
    "time": "Wed Nov 25 22:36:58 2020 +0100"
  },
  "committer": {
    "name": "Tomasz Michalak",
    "email": "tmichalak@antmicro.com",
    "time": "Thu Nov 26 14:36:08 2020 +0100"
  },
  "message": "SDC: Add dangling wires to PLL design\n\nSigned-off-by: Tomasz Michalak \u003ctmichalak@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "63542da0c14bbd419dd8dfe6b26387b12a96b1be",
      "old_mode": 33188,
      "old_path": "sdc-plugin/tests/pll/pll.v",
      "new_id": "5c401b8c59f4deb63bda207f28c2db6f5108e402",
      "new_mode": 33188,
      "new_path": "sdc-plugin/tests/pll/pll.v"
    }
  ]
}