)]}'
{
  "commit": "f85cd18a3593e50c1079cd492691a54aa96fb878",
  "tree": "0caf4e130c37b452b3f88a83b5673f9362cca355",
  "parents": [
    "dd4cf9b3109ee033a63867887c32ed8526a87774"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed May 17 11:52:31 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed May 17 11:52:31 2023 +0200"
  },
  "message": "systemverilog-plugin: split line and column in uhdmast_assert_log\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "aa511b4f4c84ab7cfa704b61955219128dfcb5c7",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "78b4869e0b1688574bd6bef3633db53b27a3a764",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}