)]}'
{
  "commit": "fa09d0fdbbb91e3fea2aa112c029bbb8a6d4cab1",
  "tree": "2f765fbb703062e93af7f02c78eecf3a8abd7c74",
  "parents": [
    "ec8843513e6083b188c0498f076b837a4e3cd670"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 13 11:25:06 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 13 11:25:06 2023 +0100"
  },
  "message": "systemverilog-plugin: fix rename of multiple instances of same primitive cell\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "356e424b38a9a67b6d287a64d7f1065f51086635",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "2ee3adbc961d3cc144aa63dfd16311c8c68e1c88",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}