)]}'
{
  "commit": "fa9c9d3d1df36b8d94cab6d0c4beb8542de2a3c2",
  "tree": "f975f14e72e87068b3d8f9575c38d75b344aeaeb",
  "parents": [
    "4a05db9778b3ac45789e682940e0be73aaa1eacf"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Thu Jun 01 11:36:16 2023 +0200"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Thu Jun 01 11:46:36 2023 +0200"
  },
  "message": "revert setting current_struct_elem\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4083df0f324183b9ffea2d4c67f36362eade9241",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "ea9ba07d9f6ac360593c1a75dc8a35a895a38ada",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}