diff --git a/design_introspection-plugin/Makefile b/design_introspection-plugin/Makefile
index 1b65892..436000e 100644
--- a/design_introspection-plugin/Makefile
+++ b/design_introspection-plugin/Makefile
@@ -5,7 +5,7 @@
 PLUGINS_DIR = $(shell yosys-config --datdir)/plugins
 
 NAME = design_introspection
-OBJS = $(NAME).o get_nets.o
+OBJS = $(NAME).o get_nets.o get_ports.o
 
 $(NAME).so: $(OBJS)
 	$(CXX) $(CXXFLAGS) $(LDFLAGS) -shared -o $@ $^ $(LDLIBS)
diff --git a/design_introspection-plugin/design_introspection.cc b/design_introspection-plugin/design_introspection.cc
index 51921b0..3ebebf9 100644
--- a/design_introspection-plugin/design_introspection.cc
+++ b/design_introspection-plugin/design_introspection.cc
@@ -19,6 +19,7 @@
  */
 
 #include "get_nets.h"
+#include "get_ports.h"
 
 USING_YOSYS_NAMESPACE
 
@@ -27,6 +28,7 @@
 struct DesignIntrospection {
     DesignIntrospection(){}
     GetNets get_nets_cmd;
+    GetPorts get_ports_cmd;
 } DesignIntrospection;
 
 
diff --git a/design_introspection-plugin/get_ports.cc b/design_introspection-plugin/get_ports.cc
new file mode 100644
index 0000000..1d616d8
--- /dev/null
+++ b/design_introspection-plugin/get_ports.cc
@@ -0,0 +1,48 @@
+#include "get_ports.h"
+
+USING_YOSYS_NAMESPACE
+
+void GetPorts::help() {
+    //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+    log("\n");
+    log("   get_ports <port_name> \n");
+    log("\n");
+    log("Get matching ports\n");
+    log("\n");
+    log("Print the output to stdout too. This is useful when all Yosys is "
+        "executed\n");
+    log("\n");
+}
+
+void GetPorts::execute(std::vector<std::string> args, RTLIL::Design* design) {
+    if (args.size() < 2) {
+	log_cmd_error("No port specified.\n");
+    }
+    RTLIL::Module* top_module = design->top_module();
+    if (top_module == nullptr) {
+	log_cmd_error("No top module detected\n");
+    }
+    // TODO handle more than one port
+    std::string port_name = args.at(1);
+    std::string port_str(port_name.size(), '\0');
+    int bit(0);
+    if (!sscanf(port_name.c_str(), "%[^[][%d]", &port_str[0], &bit)) {
+	log_error("Couldn't find port %s\n", port_name.c_str());
+    }
+
+    port_str.resize(strlen(port_str.c_str()));
+    RTLIL::IdString port_id(RTLIL::escape_id(port_str));
+    Tcl_Interp* interp = yosys_get_tcl_interp();
+    if (auto wire = top_module->wire(port_id)) {
+	if (wire->port_input || wire->port_output) {
+	    if (bit >= wire->start_offset &&
+	        bit < wire->start_offset + wire->width) {
+		Tcl_Obj* tcl_string = Tcl_NewStringObj(port_name.c_str(), -1);
+		Tcl_SetObjResult(interp, tcl_string);
+		log("Found port %s\n", port_name.c_str());
+		return;
+	    }
+	}
+    }
+    log_error("Couldn't find port %s\n", port_name.c_str());
+}
diff --git a/design_introspection-plugin/get_ports.h b/design_introspection-plugin/get_ports.h
new file mode 100644
index 0000000..72f3c91
--- /dev/null
+++ b/design_introspection-plugin/get_ports.h
@@ -0,0 +1,11 @@
+#include "kernel/register.h"
+
+USING_YOSYS_NAMESPACE
+
+struct GetPorts : public Pass {
+	GetPorts() : Pass("get_ports", "Print matching ports") {}
+
+	void help() override;
+
+	void execute(std::vector<std::string> args, RTLIL::Design* design) override;
+};
diff --git a/xdc-plugin/xdc.cc b/xdc-plugin/xdc.cc
index 8dd72c2..a27bdf7 100644
--- a/xdc-plugin/xdc.cc
+++ b/xdc-plugin/xdc.cc
@@ -71,57 +71,6 @@
 	Tcl_Eval(interp, tcl_script.c_str());
 }
 
-struct GetPorts : public Pass {
-	GetPorts() : Pass("get_ports", "Print matching ports") {
-		register_in_tcl_interpreter(pass_name);
-	}
-
-	void help() override
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("   get_ports <port_name> \n");
-		log("\n");
-		log("Get matching ports\n");
-		log("\n");
-		log("Print the output to stdout too. This is useful when all Yosys is executed\n");
-		log("\n");
-	}
-
-	void execute(std::vector<std::string> args, RTLIL::Design* design) override
-	{
-		if (args.size() < 2) {
-			log_cmd_error("No port specified.\n");
-		}
-		RTLIL::Module* top_module = design->top_module();
-		if (top_module == nullptr) {
-			log_cmd_error("No top module detected\n");
-		}
-		// TODO handle more than one port
-		port_name = args.at(1);
-		std::string port_str(port_name.size(), '\0');
-		int bit(0);
-		if (!sscanf(port_name.c_str(), "%[^[][%d]", &port_str[0], &bit)) {
-			log_error("Couldn't find port %s\n", port_name.c_str());
-		}
-
-		port_str.resize(strlen(port_str.c_str()));
-		RTLIL::IdString port_id(RTLIL::escape_id(port_str));
-		if (auto wire = top_module->wire(port_id)) {
-			if (isInputPort(wire) || isOutputPort(wire)) {
-				if (bit >= wire->start_offset && bit < wire->start_offset + wire->width) {
-					Tcl_Interp *interp = yosys_get_tcl_interp();
-					Tcl_SetResult(interp, const_cast<char*>(port_name.c_str()), NULL);
-					log("Found port %s\n", port_name.c_str());
-					return;
-				}
-			}
-		}
-		log_error("Couldn't find port %s\n", port_name.c_str());
-	}
-	std::string port_name;
-};
-
 struct GetIOBanks : public Pass {
 	GetIOBanks(std::function<const BankTilesMap&()> get_bank_tiles)
 		: Pass("get_iobanks", "Set IO Bank number")
@@ -435,7 +384,6 @@
 	}
 
 	BankTilesMap bank_tiles;
-	struct GetPorts GetPorts;
 	struct GetIOBanks GetIOBanks;
 	struct SetProperty SetProperty;
 } ReadXdc;