diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index 9f259d5..5ac2819 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -28,7 +28,7 @@
     wire->set_string_attribute(RTLIL::escape_id("CLASS"), "clock");
     wire->set_string_attribute(RTLIL::escape_id("NAME"), name);
     wire->set_string_attribute(RTLIL::escape_id("SOURCE_PINS"),
-                               Clock::ClockWireName(wire));
+                               Clock::WireName(wire));
     wire->set_string_attribute(RTLIL::escape_id("PERIOD"),
                                std::to_string(period));
     std::string waveform(std::to_string(rising_edge) + " " +
@@ -45,7 +45,7 @@
 
 void Clock::Add(RTLIL::Wire* wire, float period, float rising_edge,
                 float falling_edge) {
-    Add(Clock::ClockWireName(wire), wire, period, rising_edge, falling_edge);
+    Add(Clock::WireName(wire), wire, period, rising_edge, falling_edge);
 }
 
 float Clock::Period(RTLIL::Wire* clock_wire) {
@@ -64,7 +64,7 @@
 	if (!period) {
 	    log_cmd_error(
 	        "Neither PERIOD nor WAVEFORM has been specified for wire %s\n",
-	        ClockWireName(clock_wire).c_str());
+	        WireName(clock_wire).c_str());
 	    return std::make_pair(0, 0);
 	}
 	float falling_edge = period / 2;
@@ -90,7 +90,14 @@
     return Waveform(clock_wire).second;
 }
 
-std::string Clock::ClockWireName(RTLIL::Wire* wire) {
+std::string Clock::Name(RTLIL::Wire* clock_wire) {
+    if (clock_wire->has_attribute(RTLIL::escape_id("NAME"))) {
+	return clock_wire->get_string_attribute(RTLIL::escape_id("NAME"));
+    }
+    return WireName(clock_wire);
+}
+
+std::string Clock::WireName(RTLIL::Wire* wire) {
     if (!wire) {
 	return std::string();
     }
@@ -98,15 +105,15 @@
     return std::regex_replace(wire_name, std::regex{"\\$"}, "\\$");
 }
 
-const std::vector<RTLIL::Wire*> Clocks::GetClocks(RTLIL::Design* design) {
-    std::vector<RTLIL::Wire*> clock_wires;
+const std::map<std::string, RTLIL::Wire*> Clocks::GetClocks(RTLIL::Design* design) {
+    std::map<std::string, RTLIL::Wire*> clock_wires;
     RTLIL::Module* top_module = design->top_module();
     for (auto& wire_obj : top_module->wires_) {
 	auto& wire = wire_obj.second;
 	if (wire->has_attribute(RTLIL::escape_id("CLOCK_SIGNAL"))) {
 	    if (wire->get_string_attribute(RTLIL::escape_id("CLOCK_SIGNAL")) ==
 	        "yes") {
-		clock_wires.push_back(wire);
+		clock_wires.insert(std::make_pair(Clock::WireName(wire), wire));
 	    }
 	}
     }
diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index 6fab3ea..d405c62 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h
@@ -18,6 +18,7 @@
 #ifndef _CLOCKS_H_
 #define _CLOCKS_H_
 
+#include <map>
 #include <vector>
 #include "buffers.h"
 #include "kernel/rtlil.h"
@@ -32,15 +33,16 @@
 class Clock {
    public:
     static void Add(const std::string& name, RTLIL::Wire* wire, float period,
-                  float rising_edge, float falling_edge);
+                    float rising_edge, float falling_edge);
     static void Add(const std::string& name, std::vector<RTLIL::Wire*> wires,
-                  float period, float rising_edge, float falling_edge);
-    static void Add(RTLIL::Wire* wire, float period,
-                  float rising_edge, float falling_edge);
+                    float period, float rising_edge, float falling_edge);
+    static void Add(RTLIL::Wire* wire, float period, float rising_edge,
+                    float falling_edge);
     static float Period(RTLIL::Wire* clock_wire);
     static float RisingEdge(RTLIL::Wire* clock_wire);
     static float FallingEdge(RTLIL::Wire* clock_wire);
-    static std::string ClockWireName(RTLIL::Wire* wire);
+    static std::string Name(RTLIL::Wire* clock_wire);
+    static std::string WireName(RTLIL::Wire* wire);
 
    private:
     static std::pair<float, float> Waveform(RTLIL::Wire* clock_wire);
@@ -48,7 +50,7 @@
 
 class Clocks {
    public:
-    static const std::vector<RTLIL::Wire*> GetClocks(RTLIL::Design* design);
+    static const std::map<std::string, RTLIL::Wire*> GetClocks(RTLIL::Design* design);
 };
 
 #endif  // _CLOCKS_H_
diff --git a/sdc-plugin/propagation.cc b/sdc-plugin/propagation.cc
index dc24d00..a2dffe2 100644
--- a/sdc-plugin/propagation.cc
+++ b/sdc-plugin/propagation.cc
@@ -21,9 +21,10 @@
 USING_YOSYS_NAMESPACE
 
 void Propagation::PropagateThroughBuffers(Buffer buffer) {
-    for (auto& clock_wire : Clocks::GetClocks(design_)) {
+    for (auto& clock : Clocks::GetClocks(design_)) {
+	auto& clock_wire = clock.second;
 #ifdef SDC_DEBUG
-	log("Clock wire %s\n", Clock::ClockWireName(clock_wire).c_str());
+	log("Clock wire %s\n", Clock::WireName(clock_wire).c_str());
 #endif
 	auto buf_wires =
 	    FindSinkWiresForCellType(clock_wire, buffer.type, buffer.output);
@@ -143,12 +144,13 @@
 #ifdef SDC_DEBUG
     log("Start natural clock propagation\n");
 #endif
-    for (auto& clock_wire : Clocks::GetClocks(design_)) {
+    for (auto& clock : Clocks::GetClocks(design_)) {
+	auto& clock_wire = clock.second;
 #ifdef SDC_DEBUG
 	log("Processing clock %s\n", RTLIL::id2cstr(clock_wire->name));
 #endif
 	auto aliases = FindAliasWires(clock_wire);
-	Clock::Add(Clock::ClockWireName(clock_wire), aliases,
+	Clock::Add(Clock::WireName(clock_wire), aliases,
 	           Clock::Period(clock_wire), Clock::RisingEdge(clock_wire),
 	           Clock::FallingEdge(clock_wire));
     }
@@ -202,9 +204,10 @@
 
 void ClockDividerPropagation::PropagateThroughClockDividers(
     ClockDivider divider) {
-    for (auto& clock_wire : Clocks::GetClocks(design_)) {
+    for (auto& clock : Clocks::GetClocks(design_)) {
+	auto& clock_wire = clock.second;
 #ifdef SDC_DEBUG
-	log("Processing clock %s\n", Clock::ClockWireName(clock_wire).c_str());
+	log("Processing clock %s\n", Clock::WireName(clock_wire).c_str());
 #endif
 	PropagateClocksForCellType(clock_wire, divider.type);
     }
diff --git a/sdc-plugin/sdc.cc b/sdc-plugin/sdc.cc
index b940301..880eeb2 100644
--- a/sdc-plugin/sdc.cc
+++ b/sdc-plugin/sdc.cc
@@ -197,13 +197,14 @@
 	if (args.size() > 1) {
 	    log_warning("Command doesn't support arguments, so they will be ignored.\n");
 	}
-	std::vector<RTLIL::Wire*> clock_wires(Clocks::GetClocks(design));
-	if (clock_wires.size() == 0) {
+	std::map<std::string, RTLIL::Wire*> clocks(Clocks::GetClocks(design));
+	if (clocks.size() == 0) {
 	    log_warning("No clocks found in design\n");
 	}
 	Tcl_Interp* interp = yosys_get_tcl_interp();
 	Tcl_Obj* tcl_list = Tcl_NewListObj(0, NULL);
-	for (auto wire : clock_wires) {
+	for (auto& clock : clocks) {
+	    auto& wire = clock.second;
 	    const char* name = RTLIL::id2cstr(wire->name);
 	    Tcl_Obj* name_obj = Tcl_NewStringObj(name, -1);
 	    Tcl_ListObjAppendElement(interp, tcl_list, name_obj);
diff --git a/sdc-plugin/sdc_writer.cc b/sdc-plugin/sdc_writer.cc
index 41ebfa3..80c8e5e 100644
--- a/sdc-plugin/sdc_writer.cc
+++ b/sdc-plugin/sdc_writer.cc
@@ -45,15 +45,16 @@
 }
 
 void SdcWriter::WriteClocks(RTLIL::Design* design, std::ostream& file) {
-    for (auto& clock_wire : Clocks::GetClocks(design)) {
+    for (auto& clock : Clocks::GetClocks(design)) {
 	// FIXME: Input port nets are not found in VPR
+	auto& clock_wire = clock.second;
 	if (clock_wire->port_input) {
 	    continue;
 	}
 	file << "create_clock -period " << Clock::Period(clock_wire);
 	file << " -waveform {" << Clock::RisingEdge(clock_wire) << " "
 	     << Clock::FallingEdge(clock_wire) << "}";
-	file << " " << Clock::ClockWireName(clock_wire);
+	file << " " << Clock::WireName(clock_wire);
 	file << std::endl;
     }
 }