Google Git
Sign in
foss-fpga-tools / yosys-symbiflow-plugins / 6b69bc5ed8eafbaca6f143062dbe0c486a8a37b3
  1. 6b69bc5 Merge pull request #488 from antmicro/tagged_pattern_struct_param by Magdalena Andrys · 2 years ago
  2. 7f0fad9 Take name from the AST_DOT node in pattern assignment by Magdalena Andrys · 2 years ago
  3. 137606e Merge pull request #487 from antmicro/kr/fix_genscope_param by Kamil Rakoczy · 2 years ago
  4. 3a440c4 Merge pull request #486 from antmicro/kr/add_file_info by Kamil Rakoczy · 2 years ago
  5. f916897 systemverilog-plugin: replace default parameter definition in genscope by Kamil Rakoczy · 2 years ago
  6. 2cbacf4 systemverilog-plugin: add information about file when we can't find ancestor for tagged pattern by Kamil Rakoczy · 2 years ago
  7. 96a0853 Merge pull request #479 from antmicro/kr/module_input_type by Kamil Rakoczy · 2 years ago
  8. 8b80abc Merge pull request #484 from hzeller/20230413-add-ys-size-type by Magdalena Andrys · 2 years ago
  9. 44f0687 Make it easy to change the type used for sizes. by Henner Zeller · 2 years ago
  10. 90117fe Merge pull request #483 from antmicro/wsip/invalidvalue by wsipak · 2 years ago
  11. 9ee0565 Merge pull request #480 from antmicro/simplify-struct-with-range by Magdalena Andrys · 2 years ago
  12. 67537a2 Warn about invalidvalue in reduceExpr by Wojciech Sipak · 2 years ago
  13. 35509c2 yosys-systemverilog: Support struct with a range in simplify by Magdalena Andrys · 2 years, 1 month ago
  14. 932ef09 Merge pull request #454 from antmicro/wsip/typeparam by wsipak · 2 years ago
  15. 82f3d4a systemverilog-plugin: apply review comment by Kamil Rakoczy · 2 years, 1 month ago
  16. 0eacedd systemverilog-plugin: apply custom simplification step to wiretype while resolving wiretype by Kamil Rakoczy · 2 years, 1 month ago
  17. 60fc56f systemverilog-plugin: dont simplify wire multiple times by Kamil Rakoczy · 2 years, 1 month ago
  18. cab19a3 systemverilog-plugin: only convert custom ranges when they exist by Kamil Rakoczy · 2 years, 1 month ago
  19. 382aabf systemverilog-plugin: fix sometimes wrong handle of ranges in port wire by Kamil Rakoczy · 2 years, 1 month ago
  20. 94d267d systemverilog-plugin: fix sometimes missing typedef in port wire by Kamil Rakoczy · 2 years, 1 month ago
  21. 794ff73 Merge pull request #481 from hzeller/20230406-no-kitchen-sink-include by Mariusz Glebocki · 2 years, 1 month ago
  22. ab67743 Be specific of what includes we need from surelog. by Henner Zeller · 2 years, 1 month ago
  23. 4b1b632 Merge pull request #475 from hzeller/20230328-use-pkg-config by Mariusz Glebocki · 2 years, 1 month ago
  24. 1e2d0b9 Merge pull request #476 from antmicro/yosys-simplify-inside-plugin by Magdalena Andrys · 2 years, 1 month ago
  25. c6cf2ce Re-add the line-continuation for cxxflag line. by Henner Zeller · 2 years, 1 month ago
  26. a9503d1 Update systemverilog-plugin/Makefile by Henner Zeller · 2 years, 1 month ago
  27. ff1a8c3 Update systemverilog-plugin/Makefile by Henner Zeller · 2 years, 1 month ago
  28. 3347171 systemverilog-plugin: Add description for simplify files in third_party/yosys by Magdalena Andrys · 2 years, 1 month ago
  29. b64bd44 systemverilog-plugin: Change the way Yosys::AST:: members are called by Magdalena Andrys · 2 years, 1 month ago
  30. eba2751 systemverilog-plugin: Add simplify.h by Magdalena Andrys · 2 years, 1 month ago
  31. bf5383e systemverilog-plugin: Update Makefile by Magdalena Andrys · 2 years, 1 month ago
  32. fa22fa8 systemverilog-plugin: Use simplify from third_party instead of the one from yosys by Magdalena Andrys · 2 years, 1 month ago
  33. 68dcbae systemverilog-plugin: Rename plugin's simplify to simplify_sv by Magdalena Andrys · 2 years, 1 month ago
  34. d5602a1 systemverilog-plugin: Use AstNode:: members correctly by Magdalena Andrys · 2 years, 1 month ago
  35. ddd1903 systemverilog-plugin: Adjusting simplify.cc, removing unneded code by Magdalena Andrys · 2 years, 1 month ago
  36. b3b04dc Process type parameters by Wojciech Sipak · 2 years, 3 months ago
  37. e7070ca Merge pull request #477 from hzeller/20230404-add-missing-include by Mariusz Glebocki · 2 years, 1 month ago
  38. 0da7e0d Merge pull request #478 from antmicro/kr/unlock_surelog by Mariusz Glebocki · 2 years, 1 month ago
  39. a97dfc1 Merge pull request #470 from antmicro/kr/union_custom_type_multirange by Kamil Rakoczy · 2 years, 1 month ago
  40. d491817 systemverilog-plugin: Add simplify.cc to third party files by Magdalena Andrys · 2 years, 1 month ago
  41. b7cce65 systemverilog-plugin: unlock surelog version by Kamil Rakoczy · 2 years, 1 month ago
  42. 392ef31 Add missing include. by Henner Zeller · 2 years, 1 month ago
  43. 81d5c28 Rename _SO_LIB to SO_LIB as it is now used beyond Makefile_plugin.common by Henner Zeller · 2 years, 1 month ago
  44. c79c095 Systemverilog plugin: Use pkg-config to determine dependencies. by Henner Zeller · 2 years, 1 month ago
  45. 3bfd401 Merge pull request #471 from antmicro/kr/fix_param_const_simplify by Mariusz Glebocki · 2 years, 1 month ago
  46. 67119f5 clear scope before setting it up again by Wojciech Sipak · 2 years, 1 month ago
  47. cbd00f0 Merge pull request #473 from antmicro/kr/fix_func by Kamil Rakoczy · 2 years, 1 month ago
  48. 8e5d56f systemverilog-plugin: delete children when changing wire to id in process_assignment by Kamil Rakoczy · 2 years, 1 month ago
  49. aa22df7 systemverilog-plugin: fix assignments to wire by Kamil Rakoczy · 2 years, 1 month ago
  50. c0a15d0 Apply review comments by Kamil Rakoczy · 2 years, 1 month ago
  51. 652f82d Merge pull request #474 from antmicro/wsip/fix_memleaks by wsipak · 2 years, 1 month ago
  52. 38a659f fix memory leaks of AstNode objects by Wojciech Sipak · 2 years, 1 month ago
  53. 1a3724a systemverilog-plugin: apply review comments by Kamil Rakoczy · 2 years, 1 month ago
  54. 0166c47 systemverilog-plugin: fix accessing 2 dimensional packed array using single range by Kamil Rakoczy · 2 years, 1 month ago
  55. 1c19ca5 systemverilog-plugin: add support for custom type with multiranges inside struct/union by Kamil Rakoczy · 2 years, 1 month ago
  56. 14d3670 Initialize and cleanup attr_ids before/after design processing. by Mariusz Glebocki · 2 years, 1 month ago
  57. 4ea2ebf systemverilog-plugin: use custom simplification step before yosys by Kamil Rakoczy · 2 years, 1 month ago
  58. 23669fb Initial refactoring of IdString handling. by Mariusz Glebocki · 2 years, 1 month ago
  59. 0a91e20 Merge pull request #468 from antmicro/wsip/reduce_expr by wsipak · 2 years, 1 month ago
  60. f53aff8 use reduceExpr to evaluate logic typespecs by Wojciech Sipak · 2 years, 2 months ago
  61. e0a923c Merge pull request #466 from antmicro/kr/process_module by Kamil Rakoczy · 2 years, 1 month ago
  62. 0c7f1c0 systemverilog-plugin: update comment by Kamil Rakoczy · 2 years, 1 month ago
  63. 83ad47a systemverilog-plugin: add assert by Kamil Rakoczy · 2 years, 1 month ago
  64. f84b823 systemverilog-plugin: refactor by Kamil Rakoczy · 2 years, 1 month ago
  65. fa09d0f systemverilog-plugin: fix rename of multiple instances of same primitive cell by Kamil Rakoczy · 2 years, 1 month ago
  66. ec88435 systemverilog-plugin: simplify module processing by Kamil Rakoczy · 2 years, 2 months ago
  67. 3b962ad systemverilog-plugin: use derived_module_name to set module name by Kamil Rakoczy · 2 years, 2 months ago
  68. 24755e3 Merge pull request #464 from antmicro/kr/negative_range by Kamil Rakoczy · 2 years, 2 months ago
  69. 35a3c3c Merge pull request #462 from antmicro/kr/wire_fix by Kamil Rakoczy · 2 years, 2 months ago
  70. 3c86f71 systemverilog-plugin: set range before range_valid by Kamil Rakoczy · 2 years, 2 months ago
  71. ab3e14f Merge pull request #461 from antmicro/memory_in_genblock_nested by Magdalena Andrys · 2 years, 2 months ago
  72. 2a74a09 systemverilog-plugin: Support memories in nested genblocks by Magdalena Andrys · 2 years, 3 months ago
  73. 8430e64 systemverilog-plugin: fix wires not starting from 0 by Kamil Rakoczy · 2 years, 2 months ago
  74. 84fe833 systemverilog-plugin: Use current scope in check memories by Kamil Rakoczy · 2 years, 3 months ago
  75. ae92491 Merge pull request #459 from antmicro/kr/remove_force_keep by Kamil Rakoczy · 2 years, 2 months ago
  76. 93f8009 Merge pull request #458 from antmicro/kr/memory_slice by Kamil Rakoczy · 2 years, 2 months ago
  77. 72e3210 systemverilog-plugin: update comment by Kamil Rakoczy · 2 years, 2 months ago
  78. 4a9727c systemverilog-plugin: remove force-keep attribute by Kamil Rakoczy · 2 years, 2 months ago
  79. f4ce648 systemverilog-plugin: convert memory when accessing slice by Kamil Rakoczy · 2 years, 2 months ago
  80. 43308c1 Merge pull request #456 from antmicro/kr/imported_func by Kamil Rakoczy · 2 years, 2 months ago
  81. 3e5df84 systemverilog-plugin: cleanup by Kamil Rakoczy · 2 years, 2 months ago
  82. ac62c63 Merge pull request #455 from antmicro/kr/imported_func by Kamil Rakoczy · 2 years, 2 months ago
  83. 0251f75 systemverilog-plugin: prefer full name in function calls by Kamil Rakoczy · 2 years, 2 months ago
  84. 5445887 systemverilog-plugin: visit only topPackages by Kamil Rakoczy · 2 years, 2 months ago
  85. 345fe14 Merge pull request #452 from antmicro/kr/add_list_op by Kamil Rakoczy · 2 years, 2 months ago
  86. 1124b53 systemverilog-plugin: apply review comments by Kamil Rakoczy · 2 years, 2 months ago
  87. 6174ed1 systemverilog-plugin: use attributes instead of custom node type by Kamil Rakoczy · 2 years, 2 months ago
  88. 28f5577 systemverilog-plugin: handle identifiers as list op arguments by Kamil Rakoczy · 2 years, 3 months ago
  89. 3a066ee systemverilog-plugin: move handle of list op to process_case_item by Kamil Rakoczy · 2 years, 3 months ago
  90. 08430ec Merge pull request #451 from antmicro/kr/casez by Kamil Rakoczy · 2 years, 3 months ago
  91. a5a59ed Merge pull request #450 from antmicro/kr/add_list_op by Kamil Rakoczy · 2 years, 3 months ago
  92. 681aa55 systemverilog-plugin: add support for case type in process_value by Kamil Rakoczy · 2 years, 3 months ago
  93. 67deb91 systemverilog: add support for list op with low and high bound by Kamil Rakoczy · 2 years, 3 months ago
  94. 0af8e42 systemverilog: casex: convert Sx to Sz to match yosys frontend by Kamil Rakoczy · 2 years, 3 months ago
  95. 79d291d systemverilog-plugin: add support for case type by Kamil Rakoczy · 2 years, 3 months ago
  96. a20c6a9 Merge pull request #382 from kanndil/clock_gating by Tomasz Michalak · 2 years, 3 months ago
  97. b5d9b3c Merge pull request #448 from chipsalliance/mglb/SdcAddMissingIncludes by Tomasz Michalak · 2 years, 3 months ago
  98. f7fe1e8 sdc-plugin: Add missing includes. by Mariusz Glebocki · 2 years, 3 months ago
  99. 7226502 Merge pull request #446 from antmicro/wsip/type_parameter by Mariusz Glebocki · 2 years, 3 months ago
  100. e97cb10 Merge pull request #447 from antmicro/rszc/skip-final-stmt by Mariusz Glebocki · 2 years, 3 months ago