| # Yosys F4PGA Plugins |
| |
| This repository contains plugins for [Yosys](https://github.com/YosysHQ/yosys.git) developed as [part of the F4PGA project](https://f4pga.org). |
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| ## Design introspection plugin |
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| Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a |
| selection of objects. |
| Additionally provides functions to convert selection on TCL lists. |
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| Following commands are added with the plugin: |
| |
| * get_cells |
| * get_nets |
| * get_pins |
| * get_ports |
| * get_count |
| * selection_to_tcl_list |
| |
| ## FASM plugin |
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| Writes out the design's [fasm features](https://fasm.readthedocs.io/en/latest/) based on the parameter annotations on a |
| design cell. |
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| The plugin adds the following command: |
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| * write_fasm |
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| ## Integrate inverters plugin |
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| Implements a pass that integrates inverters into cells that have ports with the 'invertible_pin' attribute set. |
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| The plugin adds the following command: |
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| * integrateinv |
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| ## Parameters plugin |
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| Reads the specified parameter on a selected object. |
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| The plugin adds the following command: |
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| * getparam |
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| ## QuickLogic IOB plugin |
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| [QuickLogic IOB plugin](./ql-iob-plugin/) annotates IO buffer cells with information from IO placement constraints. |
| Used during synthesis for QuickLogic EOS-S3 architecture. |
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| The plugin adds the following command: |
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| * quicklogic_iob |
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| ## QuickLogic QLF FPGAs plugin |
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| [QuickLogic QLF plugin](./ql-qlf-plugin) extends Yosys with synthesis support for `qlf_k4n8` and `qlf_k6n10` architectures. |
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| The plugin adds the following command: |
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| * synth_quicklogic |
| * ql_dsp |
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| Detailed help on the supported command(s) can be obtained by running `help <command_name>` in Yosys. |
| |
| ## SDC plugin |
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| Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the |
| complete SDC information. |
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| The plugin adds the following commands: |
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| * read_sdc |
| * write_sdc |
| * create_clock |
| * get_clocks |
| * propagate_clocks |
| * set_false_path |
| * set_max_delay |
| * set_clock_groups |
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| ## XDC plugin |
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| Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as: |
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| * INTERNAL_VREF |
| * IOSTANDARD |
| * SLEW |
| * DRIVE |
| * IN_TERM |
| * LOC |
| * PACKAGE_PIN |
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| The plugin adds the following commands: |
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| * read_xdc |
| * get_iobanks |
| * set_property |
| * get_bank_tiles |
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| ## SystemVerilog plugin |
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| Reads SystemVerilog and UHDM files and processes them into yosys AST. |
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| The plugin adds the following commands: |
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| * read_systemverilog |
| * read_uhdm |
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| Detailed help on the supported command(s) can be obtained by running `help <command_name>` in Yosys. |
