Update to prjtrellis 39b70523442c4038b5177b81eab8c8cd99cd3585 Signed-off-by: David Shah <davey1576@gmail.com>
diff --git a/ECP5/tiledata/DCU0/bits.db b/ECP5/tiledata/DCU0/bits.db index 1bfb656..d4cf9b8 100644 --- a/ECP5/tiledata/DCU0/bits.db +++ b/ECP5/tiledata/DCU0/bits.db
@@ -1,6 +1,161 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.CH0_CC_MATCH_1 0000000000 +F48B1 +F49B1 +F50B1 +F51B1 +F54B1 +F55B1 +F56B1 +F57B1 +F82B1 +F83B1 + +.config DCU.CH0_CC_MATCH_2 0000000000 +F58B1 +F59B1 +F60B1 +F61B1 +F62B1 +F63B1 +F64B1 +F65B1 +F84B1 +F85B1 + +.config DCU.CH0_CC_MATCH_3 0000000000 +F66B1 +F67B1 +F68B1 +F69B1 +F70B1 +F71B1 +F72B1 +F73B1 +F86B1 +F87B1 + +.config DCU.CH0_CC_MATCH_4 0000000000 +F74B1 +F75B1 +F76B1 +F77B1 +F78B1 +F79B1 +F80B1 +F81B1 +F88B1 +F89B1 + +.config DCU.CH0_CTC_BYPASS 0 +F36B1 + +.config DCU.CH0_DEC_BYPASS 0 +F35B1 + +.config DCU.CH0_ENABLE_CG_ALIGN 0 +F15B1 + +.config DCU.CH0_ENC_BYPASS 0 +F27B1 + +.config DCU.CH0_GE_AN_ENABLE 0 +F12B1 + +.config DCU.CH0_INVERT_RX 0 +F8B1 + +.config DCU.CH0_INVERT_TX 0 +F9B1 + +.config DCU.CH0_LSM_DISABLE 0 +F39B1 + +.config DCU.CH0_MATCH_2_ENABLE 0 +F44B1 + +.config DCU.CH0_MATCH_4_ENABLE 0 +F45B1 + +.config DCU.CH0_MIN_IPG_CNT 00 +F46B1 +F47B1 + +.config DCU.CH0_PCIE_EI_EN 0 +F22B1 + +.config DCU.CH0_PCIE_MODE 0 +F2B1 + +.config DCU.CH0_PCS_DET_TIME_SEL 00 +F20B1 +F21B1 + +.config DCU.CH0_PRBS_ENABLE 0 +F14B1 + +.config DCU.CH0_PRBS_LOCK 0 +F13B1 + +.config DCU.CH0_PRBS_SELECTION 0 +F10B1 + +.config DCU.CH0_RIO_MODE 0 +F3B1 + +.config DCU.CH0_RX_GEAR_BYPASS 0 +F37B1 + +.config DCU.CH0_RX_GEAR_MODE 0 +F19B1 + +.config DCU.CH0_RX_SB_BYPASS 0 +F33B1 + +.config DCU.CH0_SB_BYPASS 0 +F30B1 + +.config DCU.CH0_TX_GEAR_BYPASS 0 +F25B1 + +.config DCU.CH0_TX_GEAR_MODE 0 +F18B1 + +.config DCU.CH0_UC_MODE 0 +F0B1 + +.config DCU.CH0_UDF_COMMA_A 1100000000 +F98B1 +F99B1 +F100B1 +F101B1 +F102B1 +F103B1 +F104B1 +F105B1 +- +- + +.config DCU.CH0_UDF_COMMA_MASK 1100000000 +F90B1 +F91B1 +F92B1 +F93B1 +F94B1 +F95B1 +F96B1 +F97B1 +- +- + +.config DCU.CH0_WA_BYPASS 0 +F34B1 + +.config DCU.CH0_WA_MODE 0 +F4B1 + # Fixed Connections .fixed_conn CH0_RX_REFCLK_DCU CH0_RX_REFCLK
diff --git a/ECP5/tiledata/DCU1/bits.db b/ECP5/tiledata/DCU1/bits.db index d13466e..78f2cff 100644 --- a/ECP5/tiledata/DCU1/bits.db +++ b/ECP5/tiledata/DCU1/bits.db
@@ -1,5 +1,181 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.CH0_LDR_CORE2TX_SEL 0 +F27B1 + +.config DCU.CH0_LDR_RX2CORE_SEL 0 +F77B1 + +.config DCU.CH0_LEQ_OFFSET_SEL 0 +F90B1 + +.config DCU.CH0_LEQ_OFFSET_TRIM 000 +F91B1 +F92B1 +F93B1 + +.config DCU.CH0_RATE_MODE_RX 0 +F75B1 + +.config DCU.CH0_RATE_MODE_TX 0 +F25B1 + +.config DCU.CH0_RCV_DCC_EN 0 +F79B1 + +.config DCU.CH0_REQ_EN 0 +F98B1 + +.config DCU.CH0_REQ_LVL_SET 00 +F103B1 +F104B1 + +.config DCU.CH0_RPWDNB 0 +F74B1 + +.config DCU.CH0_RTERM_RX 00000 +F82B1 +F83B1 +F84B1 +F85B1 +F86B1 + +.config DCU.CH0_RTERM_TX 00000 +F32B1 +F33B1 +F34B1 +F35B1 +F36B1 + +.config DCU.CH0_RXIN_CM 00 +F88B1 +F89B1 + +.config DCU.CH0_RXTERM_CM 00 +F80B1 +F81B1 + +.config DCU.CH0_RX_DIV11_SEL 0 +F76B1 + +.config DCU.CH0_RX_RATE_SEL 0000 +F99B1 +F100B1 +F101B1 +F102B1 + +.config DCU.CH0_TDRV_DAT_SEL 00 +F70B1 +F71B1 + +.config DCU.CH0_TDRV_POST_EN 0 +F29B1 + +.config DCU.CH0_TDRV_PRE_EN 0 +F28B1 + +.config DCU.CH0_TDRV_SLICE0_CUR 000 +F58B1 +F59B1 +F60B1 + +.config DCU.CH0_TDRV_SLICE0_SEL 00 +F40B1 +F41B1 + +.config DCU.CH0_TDRV_SLICE1_CUR 000 +F61B1 +F62B1 +F63B1 + +.config DCU.CH0_TDRV_SLICE1_SEL 00 +F42B1 +F43B1 + +.config DCU.CH0_TDRV_SLICE2_CUR 00 +F64B1 +F65B1 + +.config DCU.CH0_TDRV_SLICE2_SEL 00 +F44B1 +F45B1 + +.config DCU.CH0_TDRV_SLICE3_CUR 00 +F54B1 +F55B1 + +.config DCU.CH0_TDRV_SLICE3_SEL 00 +F46B1 +F47B1 + +.config DCU.CH0_TDRV_SLICE4_CUR 00 +F56B1 +F57B1 + +.config DCU.CH0_TDRV_SLICE4_SEL 00 +F48B1 +F49B1 + +.config DCU.CH0_TDRV_SLICE5_CUR 00 +F72B1 +F73B1 + +.config DCU.CH0_TDRV_SLICE5_SEL 00 +F50B1 +F51B1 + +.config DCU.CH0_TPWDNB 0 +F24B1 + +.config DCU.CH0_TX_CM_SEL 00 +F37B1 +F38B1 + +.config DCU.CH0_TX_DIV11_SEL 0 +F26B1 + +.config DCU.CH0_TX_POST_SIGN 0 +F31B1 + +.config DCU.CH0_TX_PRE_SIGN 0 +F30B1 + +.config DCU.CH0_UDF_COMMA_A 0011111111 +- +- +- +- +- +- +- +- +F14B1 +F15B1 + +.config DCU.CH0_UDF_COMMA_B 0000000000 +F0B1 +F1B1 +F2B1 +F3B1 +F4B1 +F5B1 +F6B1 +F7B1 +F12B1 +F13B1 + +.config DCU.CH0_UDF_COMMA_MASK 0011111111 +- +- +- +- +- +- +- +- +F10B1 +F11B1 + # Fixed Connections
diff --git a/ECP5/tiledata/DCU2/bits.db b/ECP5/tiledata/DCU2/bits.db index d13466e..9836528 100644 --- a/ECP5/tiledata/DCU2/bits.db +++ b/ECP5/tiledata/DCU2/bits.db
@@ -1,5 +1,126 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.CH0_CDR_CNT4SEL 00 +F98B1 +F99B1 + +.config DCU.CH0_CDR_CNT8SEL 00 +F100B1 +F101B1 + +.config DCU.CH0_DCOATDCFG 00 +F63B1 +F64B1 + +.config DCU.CH0_DCOATDDLY 00 +F61B1 +F62B1 + +.config DCU.CH0_DCOBYPSATD 0 +F65B1 + +.config DCU.CH0_DCOCALDIV 000 +F75B1 +F76B1 +F77B1 + +.config DCU.CH0_DCOCTLGI 000 +F58B1 +F59B1 +F60B1 + +.config DCU.CH0_DCODISBDAVOID 0 +F74B1 + +.config DCU.CH0_DCOFLTDAC 00 +F90B1 +F91B1 + +.config DCU.CH0_DCOFTNRG 000 +F94B1 +F95B1 +F96B1 + +.config DCU.CH0_DCOIOSTUNE 000 +F71B1 +F72B1 +F73B1 + +.config DCU.CH0_DCOITUNE 00 +F92B1 +F93B1 + +.config DCU.CH0_DCOITUNE4LSB 000 +F68B1 +F69B1 +F70B1 + +.config DCU.CH0_DCOIUPDNX2 0 +F81B1 + +.config DCU.CH0_DCONUOFLSB 000 +F78B1 +F79B1 +F80B1 + +.config DCU.CH0_DCOSCALEI 00 +F66B1 +F67B1 + +.config DCU.CH0_DCOSTARTVAL 000 +F84B1 +F85B1 +F86B1 + +.config DCU.CH0_DCOSTEP 00 +F82B1 +F83B1 + +.config DCU.CH0_FF_RX_F_CLK_DIS 0 +F42B1 + +.config DCU.CH0_FF_RX_H_CLK_EN 0 +F41B1 + +.config DCU.CH0_FF_TX_F_CLK_DIS 0 +F44B1 + +.config DCU.CH0_FF_TX_H_CLK_EN 0 +F43B1 + +.config DCU.CH0_PDEN_SEL 0 +F3B1 + +.config DCU.CH0_RLOS_SEL 0 +F15B1 + +.config DCU.CH0_RX_DCO_CK_DIV 000 +F0B1 +F1B1 +F2B1 + +.config DCU.CH0_RX_LOS_CEQ 00 +F11B1 +F12B1 + +.config DCU.CH0_RX_LOS_EN 0 +F14B1 + +.config DCU.CH0_RX_LOS_HYST_EN 0 +F13B1 + +.config DCU.CH0_RX_LOS_LVL 000 +F8B1 +F9B1 +F10B1 + +.config DCU.CH0_SEL_SD_RX_CLK 0 +F40B1 + +.config_enum DCU.MODE NONE +DCUA F6B1 F7B1 +NONE - + # Fixed Connections
diff --git a/ECP5/tiledata/DCU3/bits.db b/ECP5/tiledata/DCU3/bits.db index d13466e..6344a84 100644 --- a/ECP5/tiledata/DCU3/bits.db +++ b/ECP5/tiledata/DCU3/bits.db
@@ -1,5 +1,158 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.CH0_AUTO_CALIB_EN 0 +F7B1 + +.config DCU.CH0_AUTO_FACQ_EN 0 +F6B1 + +.config DCU.CH0_BAND_THRESHOLD 000000 +F0B1 +F1B1 +F2B1 +F3B1 +F4B1 +F5B1 + +.config DCU.CH0_CALIB_CK_MODE 0 +F8B1 + +.config DCU.CH0_REG_BAND_OFFSET 0000 +F9B1 +F10B1 +F11B1 +F12B1 + +.config DCU.CH0_REG_BAND_SEL 000000 +F16B1 +F17B1 +F18B1 +F19B1 +F20B1 +F21B1 + +.config DCU.CH0_REG_IDAC_EN 0 +F34B1 + +.config DCU.CH0_REG_IDAC_SEL 0000000000 +F24B1 +F25B1 +F26B1 +F27B1 +F28B1 +F29B1 +F30B1 +F31B1 +F32B1 +F33B1 + +.config DCU.CH1_CC_MATCH_1 1100000000 +F90B1 +F91B1 +F92B1 +F93B1 +F94B1 +F95B1 +F96B1 +F97B1 +- +- + +.config DCU.CH1_CC_MATCH_2 1100000000 +F98B1 +F99B1 +F100B1 +F101B1 +F102B1 +F103B1 +F104B1 +F105B1 +- +- + +.config DCU.CH1_CTC_BYPASS 0 +F78B1 + +.config DCU.CH1_DEC_BYPASS 0 +F77B1 + +.config DCU.CH1_ENABLE_CG_ALIGN 0 +F57B1 + +.config DCU.CH1_ENC_BYPASS 0 +F69B1 + +.config DCU.CH1_GE_AN_ENABLE 0 +F54B1 + +.config DCU.CH1_INVERT_RX 0 +F48B1 + +.config DCU.CH1_INVERT_TX 0 +F49B1 + +.config DCU.CH1_LSM_DISABLE 0 +F81B1 + +.config DCU.CH1_MATCH_2_ENABLE 0 +F86B1 + +.config DCU.CH1_MATCH_4_ENABLE 0 +F87B1 + +.config DCU.CH1_MIN_IPG_CNT 00 +F88B1 +F89B1 + +.config DCU.CH1_PCIE_EI_EN 0 +F64B1 + +.config DCU.CH1_PCIE_MODE 0 +F42B1 + +.config DCU.CH1_PCS_DET_TIME_SEL 00 +F62B1 +F63B1 + +.config DCU.CH1_PRBS_ENABLE 0 +F56B1 + +.config DCU.CH1_PRBS_LOCK 0 +F55B1 + +.config DCU.CH1_PRBS_SELECTION 0 +F50B1 + +.config DCU.CH1_RIO_MODE 0 +F43B1 + +.config DCU.CH1_RX_GEAR_BYPASS 0 +F79B1 + +.config DCU.CH1_RX_GEAR_MODE 0 +F61B1 + +.config DCU.CH1_RX_SB_BYPASS 0 +F75B1 + +.config DCU.CH1_SB_BYPASS 0 +F72B1 + +.config DCU.CH1_TX_GEAR_BYPASS 0 +F67B1 + +.config DCU.CH1_TX_GEAR_MODE 0 +F60B1 + +.config DCU.CH1_UC_MODE 0 +F40B1 + +.config DCU.CH1_WA_BYPASS 0 +F76B1 + +.config DCU.CH1_WA_MODE 0 +F44B1 + # Fixed Connections
diff --git a/ECP5/tiledata/DCU4/bits.db b/ECP5/tiledata/DCU4/bits.db index d13466e..c7a66f1 100644 --- a/ECP5/tiledata/DCU4/bits.db +++ b/ECP5/tiledata/DCU4/bits.db
@@ -1,5 +1,170 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.CH1_CC_MATCH_1 0011111111 +- +- +- +- +- +- +- +- +F16B1 +F17B1 + +.config DCU.CH1_CC_MATCH_2 0011111111 +- +- +- +- +- +- +- +- +F18B1 +F19B1 + +.config DCU.CH1_CC_MATCH_3 0000000000 +F0B1 +F1B1 +F2B1 +F3B1 +F4B1 +F5B1 +F6B1 +F7B1 +F20B1 +F21B1 + +.config DCU.CH1_CC_MATCH_4 0000000000 +F8B1 +F9B1 +F10B1 +F11B1 +F12B1 +F13B1 +F14B1 +F15B1 +F22B1 +F23B1 + +.config DCU.CH1_LDR_CORE2TX_SEL 0 +F69B1 + +.config DCU.CH1_RATE_MODE_TX 0 +F67B1 + +.config DCU.CH1_RTERM_TX 00000 +F74B1 +F75B1 +F76B1 +F77B1 +F78B1 + +.config DCU.CH1_TDRV_POST_EN 0 +F71B1 + +.config DCU.CH1_TDRV_PRE_EN 0 +F70B1 + +.config DCU.CH1_TDRV_SLICE0_CUR 000 +F98B1 +F99B1 +F100B1 + +.config DCU.CH1_TDRV_SLICE0_SEL 00 +F82B1 +F83B1 + +.config DCU.CH1_TDRV_SLICE1_CUR 000 +F101B1 +F102B1 +F103B1 + +.config DCU.CH1_TDRV_SLICE1_SEL 00 +F84B1 +F85B1 + +.config DCU.CH1_TDRV_SLICE2_CUR 00 +F104B1 +F105B1 + +.config DCU.CH1_TDRV_SLICE2_SEL 00 +F86B1 +F87B1 + +.config DCU.CH1_TDRV_SLICE3_CUR 00 +F94B1 +F95B1 + +.config DCU.CH1_TDRV_SLICE3_SEL 00 +F88B1 +F89B1 + +.config DCU.CH1_TDRV_SLICE4_CUR 00 +F96B1 +F97B1 + +.config DCU.CH1_TDRV_SLICE4_SEL 00 +F90B1 +F91B1 + +.config DCU.CH1_TDRV_SLICE5_SEL 00 +F92B1 +F93B1 + +.config DCU.CH1_TPWDNB 0 +F66B1 + +.config DCU.CH1_TX_CM_SEL 00 +F79B1 +F80B1 + +.config DCU.CH1_TX_DIV11_SEL 0 +F68B1 + +.config DCU.CH1_TX_POST_SIGN 0 +F73B1 + +.config DCU.CH1_TX_PRE_SIGN 0 +F72B1 + +.config DCU.CH1_UDF_COMMA_A 0000000000 +F32B1 +F33B1 +F34B1 +F35B1 +F36B1 +F37B1 +F38B1 +F39B1 +F56B1 +F57B1 + +.config DCU.CH1_UDF_COMMA_B 0000000000 +F40B1 +F41B1 +F42B1 +F43B1 +F44B1 +F45B1 +F46B1 +F47B1 +F54B1 +F55B1 + +.config DCU.CH1_UDF_COMMA_MASK 0000000000 +F24B1 +F25B1 +F26B1 +F27B1 +F28B1 +F29B1 +F30B1 +F31B1 +F50B1 +F51B1 + # Fixed Connections
diff --git a/ECP5/tiledata/DCU5/bits.db b/ECP5/tiledata/DCU5/bits.db index d13466e..fbe61d7 100644 --- a/ECP5/tiledata/DCU5/bits.db +++ b/ECP5/tiledata/DCU5/bits.db
@@ -1,5 +1,125 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.CH1_DCOATDCFG 00 +F103B1 +F104B1 + +.config DCU.CH1_DCOATDDLY 00 +F101B1 +F102B1 + +.config DCU.CH1_DCOBYPSATD 0 +F105B1 + +.config DCU.CH1_DCOCTLGI 000 +F98B1 +F99B1 +F100B1 + +.config DCU.CH1_FF_RX_F_CLK_DIS 0 +F84B1 + +.config DCU.CH1_FF_RX_H_CLK_EN 0 +F83B1 + +.config DCU.CH1_FF_TX_F_CLK_DIS 0 +F86B1 + +.config DCU.CH1_FF_TX_H_CLK_EN 0 +F85B1 + +.config DCU.CH1_LDR_RX2CORE_SEL 0 +F11B1 + +.config DCU.CH1_LEQ_OFFSET_SEL 0 +F24B1 + +.config DCU.CH1_LEQ_OFFSET_TRIM 000 +F25B1 +F26B1 +F27B1 + +.config DCU.CH1_PDEN_SEL 0 +F43B1 + +.config DCU.CH1_RATE_MODE_RX 0 +F9B1 + +.config DCU.CH1_RCV_DCC_EN 0 +F13B1 + +.config DCU.CH1_REQ_EN 0 +F32B1 + +.config DCU.CH1_REQ_LVL_SET 00 +F37B1 +F38B1 + +.config DCU.CH1_RLOS_SEL 0 +F57B1 + +.config DCU.CH1_RPWDNB 0 +F8B1 + +.config DCU.CH1_RTERM_RX 00000 +F16B1 +F17B1 +F18B1 +F19B1 +F20B1 + +.config DCU.CH1_RXIN_CM 00 +F22B1 +F23B1 + +.config DCU.CH1_RXTERM_CM 00 +F14B1 +F15B1 + +.config DCU.CH1_RX_DCO_CK_DIV 000 +F40B1 +F41B1 +F42B1 + +.config DCU.CH1_RX_DIV11_SEL 0 +F10B1 + +.config DCU.CH1_RX_LOS_CEQ 00 +F51B1 +F54B1 + +.config DCU.CH1_RX_LOS_EN 0 +F56B1 + +.config DCU.CH1_RX_LOS_HYST_EN 0 +F55B1 + +.config DCU.CH1_RX_LOS_LVL 000 +F48B1 +F49B1 +F50B1 + +.config DCU.CH1_RX_RATE_SEL 0000 +F33B1 +F34B1 +F35B1 +F36B1 + +.config DCU.CH1_SEL_SD_RX_CLK 0 +F82B1 + +.config DCU.CH1_TDRV_DAT_SEL 00 +F4B1 +F5B1 + +.config DCU.CH1_TDRV_SLICE5_CUR 00 +F6B1 +F7B1 + +.config_enum DCU.MODE NONE +DCUA F46B1 F47B1 +NONE - + # Fixed Connections
diff --git a/ECP5/tiledata/DCU6/bits.db b/ECP5/tiledata/DCU6/bits.db index d13466e..ce9488a 100644 --- a/ECP5/tiledata/DCU6/bits.db +++ b/ECP5/tiledata/DCU6/bits.db
@@ -1,5 +1,126 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.CH1_AUTO_CALIB_EN 0 +F47B1 + +.config DCU.CH1_AUTO_FACQ_EN 0 +F46B1 + +.config DCU.CH1_BAND_THRESHOLD 000000 +F40B1 +F41B1 +F42B1 +F43B1 +F44B1 +F45B1 + +.config DCU.CH1_CALIB_CK_MODE 0 +F48B1 + +.config DCU.CH1_CDR_CNT4SEL 00 +F32B1 +F33B1 + +.config DCU.CH1_CDR_CNT8SEL 00 +F34B1 +F35B1 + +.config DCU.CH1_DCOCALDIV 000 +F9B1 +F10B1 +F11B1 + +.config DCU.CH1_DCODISBDAVOID 0 +F8B1 + +.config DCU.CH1_DCOFLTDAC 00 +F24B1 +F25B1 + +.config DCU.CH1_DCOFTNRG 000 +F28B1 +F29B1 +F30B1 + +.config DCU.CH1_DCOIOSTUNE 000 +F5B1 +F6B1 +F7B1 + +.config DCU.CH1_DCOITUNE 00 +F26B1 +F27B1 + +.config DCU.CH1_DCOITUNE4LSB 000 +F2B1 +F3B1 +F4B1 + +.config DCU.CH1_DCOIUPDNX2 0 +F15B1 + +.config DCU.CH1_DCONUOFLSB 000 +F12B1 +F13B1 +F14B1 + +.config DCU.CH1_DCOSCALEI 00 +F0B1 +F1B1 + +.config DCU.CH1_DCOSTARTVAL 000 +F18B1 +F19B1 +F20B1 + +.config DCU.CH1_DCOSTEP 00 +F16B1 +F17B1 + +.config DCU.CH1_REG_BAND_OFFSET 0000 +F49B1 +F50B1 +F51B1 +F54B1 + +.config DCU.CH1_REG_BAND_SEL 000000 +F58B1 +F59B1 +F60B1 +F61B1 +F62B1 +F63B1 + +.config DCU.CH1_REG_IDAC_EN 0 +F76B1 + +.config DCU.CH1_REG_IDAC_SEL 0000000000 +F66B1 +F67B1 +F68B1 +F69B1 +F70B1 +F71B1 +F72B1 +F73B1 +F74B1 +F75B1 + +.config DCU.D_HIGH_MARK 0000 +F102B1 +F103B1 +F104B1 +F105B1 + +.config DCU.D_LOW_MARK 0000 +F98B1 +F99B1 +F100B1 +F101B1 + +.config DCU.D_XGE_MODE 0 +F86B1 + # Fixed Connections
diff --git a/ECP5/tiledata/DCU7/bits.db b/ECP5/tiledata/DCU7/bits.db index d13466e..cda4abe 100644 --- a/ECP5/tiledata/DCU7/bits.db +++ b/ECP5/tiledata/DCU7/bits.db
@@ -1,5 +1,56 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.D_BITCLK_FROM_ND_EN 0 +F95B1 + +.config DCU.D_BITCLK_LOCAL_EN 0 +F93B1 + +.config DCU.D_BITCLK_ND_EN 0 +F94B1 + +.config DCU.D_BUS8BIT_SEL 0 +F72B1 + +.config DCU.D_CDR_LOL_SET 00 +F74B1 +F75B1 + +.config DCU.D_PLL_LOL_SET 00 +F85B1 +F86B1 + +.config DCU.D_REFCK_MODE 000 +F66B1 +F67B1 +F73B1 + +.config DCU.D_RG_EN 0 +F87B1 + +.config DCU.D_RG_SET 00 +F88B1 +F89B1 + +.config DCU.D_SETPLLRC 000000 +F76B1 +F77B1 +F78B1 +F79B1 +F80B1 +F81B1 + +.config DCU.D_SYNC_LOCAL_EN 0 +F96B1 + +.config DCU.D_SYNC_ND_EN 0 +F97B1 + +.config DCU.D_TX_VCO_CK_DIV 000 +F82B1 +F83B1 +F84B1 + # Fixed Connections
diff --git a/ECP5/tiledata/DCU8/bits.db b/ECP5/tiledata/DCU8/bits.db index d13466e..b084fc2 100644 --- a/ECP5/tiledata/DCU8/bits.db +++ b/ECP5/tiledata/DCU8/bits.db
@@ -1,5 +1,109 @@ # Routing Mux Bits # Non-Routing Configuration +.config DCU.D_BITCLK_FROM_ND_EN 0 +F0B1 + +.config DCU.D_CMUSETBIASI 00 +F76B1 +F77B1 + +.config DCU.D_CMUSETI4CPP 0000 +F66B1 +F67B1 +F68B1 +F69B1 + +.config DCU.D_CMUSETI4CPZ 0000 +F61B1 +F62B1 +F63B1 +F64B1 + +.config DCU.D_CMUSETI4VCO 00 +F43B1 +F44B1 + +.config DCU.D_CMUSETICP4P 00 +F74B1 +F75B1 + +.config DCU.D_CMUSETICP4Z 000 +F70B1 +F71B1 +F72B1 + +.config DCU.D_CMUSETINITVCT 00 +F45B1 +F46B1 + +.config DCU.D_CMUSETISCL4VCO 000 +F40B1 +F41B1 +F42B1 + +.config DCU.D_CMUSETP1GM 000 +F58B1 +F59B1 +F60B1 + +.config DCU.D_CMUSETP2AGM 000 +F51B1 +F54B1 +F55B1 + +.config DCU.D_CMUSETZGM 000 +F48B1 +F49B1 +F50B1 + +.config DCU.D_DCO_CALIB_TIME_SEL 00 +F98B1 +F99B1 + +.config DCU.D_IB_PWDNB 0 +F6B1 + +.config DCU.D_ISETLOS 00000000 +F32B1 +F33B1 +F34B1 +F35B1 +F36B1 +F37B1 +F38B1 +F39B1 + +.config DCU.D_MACROPDB 0 +F3B1 + +.config DCU.D_PD_ISET 00 +F93B1 +F94B1 + +.config DCU.D_REQ_ISET 000 +F90B1 +F91B1 +F92B1 + +.config DCU.D_SETICONST_AUX 00 +F84B1 +F85B1 + +.config DCU.D_SETICONST_CH 00 +F88B1 +F89B1 + +.config DCU.D_SETIRPOLY_AUX 00 +F82B1 +F83B1 + +.config DCU.D_SETIRPOLY_CH 00 +F86B1 +F87B1 + +.config DCU.D_TXPLL_PWDNB 0 +F5B1 + # Fixed Connections