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foss-fpga-tools/prjtrellis-db/41759ec4c83a34522f36f476108510f8e9eedd24^!/.
commit
41759ec4c83a34522f36f476108510f8e9eedd24
[log]
author
David Shah <dave@ds0.me>
Sat Feb 09 19:16:37 2019 +0000
committer
David Shah <dave@ds0.me>
Sat Feb 09 19:16:37 2019 +0000
tree
6ec1762e24a8978eefc855249d71ae51f258c00f
parent
d9603500f4a4df5b643c790d0e44bf7c67b755d0 [diff]
Fix DSP config bits

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/ECP5/tiledata/DSP_SPINE_UL0/bits.db b/ECP5/tiledata/DSP_SPINE_UL0/bits.db
index 64aeaf0..21292b1 100644
--- a/ECP5/tiledata/DSP_SPINE_UL0/bits.db
+++ b/ECP5/tiledata/DSP_SPINE_UL0/bits.db

@@ -107,6 +107,10 @@
 ALU54B F55B0 F61B0
 NONE -
 
+.config_enum MULT18_5.MODE NONE
+MULT18X18D F56B0 F57B0
+NONE -
+
 .config_enum MULT18_5.REG_INPUTB_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/DSP_SPINE_UR0/bits.db b/ECP5/tiledata/DSP_SPINE_UR0/bits.db
index 64aeaf0..21292b1 100644
--- a/ECP5/tiledata/DSP_SPINE_UR0/bits.db
+++ b/ECP5/tiledata/DSP_SPINE_UR0/bits.db

@@ -107,6 +107,10 @@
 ALU54B F55B0 F61B0
 NONE -
 
+.config_enum MULT18_5.MODE NONE
+MULT18X18D F56B0 F57B0
+NONE -
+
 .config_enum MULT18_5.REG_INPUTB_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/DSP_SPINE_UR1/bits.db b/ECP5/tiledata/DSP_SPINE_UR1/bits.db
index 64aeaf0..21292b1 100644
--- a/ECP5/tiledata/DSP_SPINE_UR1/bits.db
+++ b/ECP5/tiledata/DSP_SPINE_UR1/bits.db

@@ -107,6 +107,10 @@
 ALU54B F55B0 F61B0
 NONE -
 
+.config_enum MULT18_5.MODE NONE
+MULT18X18D F56B0 F57B0
+NONE -
+
 .config_enum MULT18_5.REG_INPUTB_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB2_DSP0/bits.db b/ECP5/tiledata/MIB2_DSP0/bits.db
index 75e36d9..feaddd7 100644
--- a/ECP5/tiledata/MIB2_DSP0/bits.db
+++ b/ECP5/tiledata/MIB2_DSP0/bits.db

@@ -252,6 +252,10 @@
 CLK3 F36B1 F37B1
 NONE -
 
+.config_enum MULT18_0.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_0.REG_PIPELINE_CLK CLK3
 CLK0 -
 CLK1 -
@@ -263,6 +267,10 @@
 OFF F34B1 F35B1 F36B1 F37B1
 ON -
 
+.config_enum MULT18_1.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_1.REG_INPUTA_CE CE3
 CE0 F4B1 F5B1 F17B1 F18B1 F23B1 F24B1 F25B1 F29B1 F41B1 F42B1
 CE1 F5B1 F18B1 F24B1 F29B1 F42B1

diff --git a/ECP5/tiledata/MIB2_DSP4/bits.db b/ECP5/tiledata/MIB2_DSP4/bits.db
index 3bd11a0..43c87c7 100644
--- a/ECP5/tiledata/MIB2_DSP4/bits.db
+++ b/ECP5/tiledata/MIB2_DSP4/bits.db

@@ -230,6 +230,10 @@
 CE2 F8B1 F26B1 F30B1 F36B1
 CE3 -
 
+.config_enum MULT18_1.MODE NONE
+MULT18X18D F4B1
+NONE -
+
 .config_enum MULT18_1.REG_PIPELINE_CLK CLK3
 CLK0 -
 CLK1 -
@@ -241,6 +245,10 @@
 OFF -
 ON F69B1 F70B1
 
+.config_enum MULT18_4.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_4.REG_PIPELINE_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB2_DSP5/bits.db b/ECP5/tiledata/MIB2_DSP5/bits.db
index bedfcab..2cdfe14 100644
--- a/ECP5/tiledata/MIB2_DSP5/bits.db
+++ b/ECP5/tiledata/MIB2_DSP5/bits.db

@@ -266,6 +266,10 @@
 CLK3 -
 NONE F21B1
 
+.config_enum MULT18_4.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_4.REG_INPUTA_RST RST3
 RST0 F100B1 F101B1
 RST1 F101B1
@@ -283,6 +287,10 @@
 ASYNC F93B1
 SYNC -
 
+.config_enum MULT18_5.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_5.REG_INPUTA_CE CE3
 CE0 F39B1
 CE1 F39B1

diff --git a/ECP5/tiledata/MIB2_DSP8/bits.db b/ECP5/tiledata/MIB2_DSP8/bits.db
index f557b63..9467085 100644
--- a/ECP5/tiledata/MIB2_DSP8/bits.db
+++ b/ECP5/tiledata/MIB2_DSP8/bits.db

@@ -244,6 +244,10 @@
 OFF -
 ON F18B1 F19B1
 
+.config_enum MULT18_5.MODE NONE
+MULT18X18D F56B1
+NONE -
+
 .config_enum MULT18_5.REG_PIPELINE_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB_DSP0/bits.db b/ECP5/tiledata/MIB_DSP0/bits.db
index a160f6e..2d9643c 100644
--- a/ECP5/tiledata/MIB_DSP0/bits.db
+++ b/ECP5/tiledata/MIB_DSP0/bits.db

@@ -77,6 +77,10 @@
 ALU54B F61B0 F64B0 F67B0 F68B0
 NONE -
 
+.config_enum MULT18_0.MODE NONE
+MULT18X18D F62B0 F65B0
+NONE -
+
 .config_enum MULT18_0.REG_INPUTA_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB_DSP1/bits.db b/ECP5/tiledata/MIB_DSP1/bits.db
index 48faed4..ee4900e 100644
--- a/ECP5/tiledata/MIB_DSP1/bits.db
+++ b/ECP5/tiledata/MIB_DSP1/bits.db

@@ -16,6 +16,10 @@
 DISABLED F61B0
 ENABLED -
 
+.config_enum MULT18_0.MODE NONE
+MULT18X18D F51B0
+NONE -
+
 .config_enum MULT18_1.GSR ENABLED
 DISABLED F61B0
 ENABLED -

diff --git a/ECP5/tiledata/MIB_DSP2/bits.db b/ECP5/tiledata/MIB_DSP2/bits.db
index 0774a02..8ea4859 100644
--- a/ECP5/tiledata/MIB_DSP2/bits.db
+++ b/ECP5/tiledata/MIB_DSP2/bits.db

@@ -377,6 +377,10 @@
 DISABLED F60B0
 ENABLED -
 
+.config_enum MULT18_0.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_0.REG_INPUTA_CLK CLK3
 CLK0 -
 CLK1 -
@@ -434,6 +438,10 @@
 DISABLED F60B0
 ENABLED -
 
+.config_enum MULT18_1.MODE NONE
+MULT18X18D F26B0
+NONE -
+
 .config_enum MULT18_1.REG_INPUTA_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB_DSP4/bits.db b/ECP5/tiledata/MIB_DSP4/bits.db
index a8bbb1e..fbcae86 100644
--- a/ECP5/tiledata/MIB_DSP4/bits.db
+++ b/ECP5/tiledata/MIB_DSP4/bits.db

@@ -107,6 +107,10 @@
 CE3 F49B0
 INV -
 
+.config_enum MULT18_1.MODE NONE
+MULT18X18D F35B0 F36B0
+NONE -
+
 .config_enum MULT18_1.REG_INPUTB_CLK CLK3
 CLK0 -
 CLK1 -
@@ -152,6 +156,10 @@
 CE3 F61B0
 INV -
 
+.config_enum MULT18_4.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_4.RST0MUX INV
 INV -
 RST0 F50B0

diff --git a/ECP5/tiledata/MIB_DSP5/bits.db b/ECP5/tiledata/MIB_DSP5/bits.db
index ee2d692..eb57a23 100644
--- a/ECP5/tiledata/MIB_DSP5/bits.db
+++ b/ECP5/tiledata/MIB_DSP5/bits.db

@@ -73,6 +73,10 @@
 CLK3 -
 NONE F56B0
 
+.config_enum MULT18_4.MODE NONE
+MULT18X18D F6B0 F9B0 F104B0
+NONE -
+
 .config_enum MULT18_4.REG_INPUTA_CLK CLK3
 CLK0 -
 CLK1 -
@@ -94,6 +98,10 @@
 CLK3 -
 NONE F57B0
 
+.config_enum MULT18_5.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_5.REG_INPUTC_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB_DSP6/bits.db b/ECP5/tiledata/MIB_DSP6/bits.db
index dcfdc54..d8cbace 100644
--- a/ECP5/tiledata/MIB_DSP6/bits.db
+++ b/ECP5/tiledata/MIB_DSP6/bits.db

@@ -153,6 +153,10 @@
 DISABLED F46B0
 ENABLED -
 
+.config_enum MULT18_4.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_4.REG_INPUTB_CLK CLK3
 CLK0 -
 CLK1 -
@@ -164,6 +168,10 @@
 DISABLED F46B0
 ENABLED -
 
+.config_enum MULT18_5.MODE NONE
+MULT18X18D F79B0
+NONE -
+
 .config_enum MULT18_5.REG_INPUTA_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB_DSP7/bits.db b/ECP5/tiledata/MIB_DSP7/bits.db
index aecbec0..25c2780 100644
--- a/ECP5/tiledata/MIB_DSP7/bits.db
+++ b/ECP5/tiledata/MIB_DSP7/bits.db

@@ -68,6 +68,10 @@
 DISABLED F4B0
 ENABLED -
 
+.config_enum MULT18_4.MODE MULT18X18D
+MULT18X18D -
+NONE -
+
 .config_enum MULT18_4.REG_INPUTA_CLK CLK3
 CLK0 -
 CLK1 -

diff --git a/ECP5/tiledata/MIB_DSP8/bits.db b/ECP5/tiledata/MIB_DSP8/bits.db
index b9db61e..fb773d9 100644
--- a/ECP5/tiledata/MIB_DSP8/bits.db
+++ b/ECP5/tiledata/MIB_DSP8/bits.db

@@ -59,6 +59,10 @@
 ALU54B F55B0 F61B0
 NONE -
 
+.config_enum MULT18_5.MODE NONE
+MULT18X18D F56B0 F57B0
+NONE -
+
 .config_enum MULT18_5.REG_INPUTB_CLK CLK3
 CLK0 -
 CLK1 -