Update to prjtrellis 5992d139b2e48b83b3a9e6904cb1f2789ce6ccad Signed-off-by: David Shah <dave@ds0.me>
diff --git a/ECP5/timing/speed_6/cells.json b/ECP5/timing/speed_6/cells.json index a253f86..e40276e 100644 --- a/ECP5/timing/speed_6/cells.json +++ b/ECP5/timing/speed_6/cells.json
@@ -13957,6 +13957,665 @@ "type": "IOPath" } ], + "IOLOGIC:MODE=IDDRX1F": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 235, + 235, + 235 + ], + "pin": "DI", + "setup": [ + 401, + 401, + 401 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "falling": [ + 356, + 356, + 356 + ], + "from_pin": "CLK", + "rising": [ + 356, + 356, + 356 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 356, + 356, + 356 + ], + "from_pin": "CLK", + "rising": [ + 356, + 356, + 356 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IDDRX2F": [ + { + "clock": [ + "negedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1799, + 1799, + 1799 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": [ + "posedge", + "ECLK" + ], + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "hold": [ + 12, + 12, + 12 + ], + "pin": "DI", + "setup": [ + 445, + 445, + 445 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1799, + 1799, + 1799 + ] + }, + { + "falling": [ + 453, + 453, + 453 + ], + "from_pin": "CLK", + "rising": [ + 453, + 453, + 453 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 453, + 453, + 453 + ], + "from_pin": "CLK", + "rising": [ + 453, + 453, + 453 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + }, + { + "falling": [ + 453, + 453, + 453 + ], + "from_pin": "CLK", + "rising": [ + 453, + 453, + 453 + ], + "to_pin": "RXDATA2", + "type": "IOPath" + }, + { + "falling": [ + 453, + 453, + 453 + ], + "from_pin": "CLK", + "rising": [ + 453, + 453, + 453 + ], + "to_pin": "RXDATA3", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IREG": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 1945, + 1945, + 1945 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "LSR", + "setup": [ + 128, + 128, + 128 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 311, + 311, + 311 + ], + "pin": "DI", + "setup": [ + 439, + 439, + 439 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 77, + 77, + 77 + ], + "pin": "CE", + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 1945, + 1945, + 1945 + ] + }, + { + "falling": [ + 474, + 474, + 474 + ], + "from_pin": "CLK", + "rising": [ + 474, + 474, + 474 + ], + "to_pin": "INFF", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=ODDRX1F": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "falling": [ + 983, + 985, + 987 + ], + "from_pin": "CLK", + "rising": [ + 983, + 985, + 987 + ], + "to_pin": "IOLDO", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=ODDRX2F": [ + { + "clock": [ + "negedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1600, + 1600, + 1600 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA0", + "setup": [ + 113, + 113, + 113 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA1", + "setup": [ + 113, + 113, + 113 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA2", + "setup": [ + 113, + 113, + 113 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA3", + "setup": [ + 113, + 113, + 113 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": [ + "posedge", + "CLK" + ], + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1600, + 1600, + 1600 + ] + }, + { + "falling": [ + 1287, + 1295, + 1303 + ], + "from_pin": "ECLK", + "rising": [ + 1287, + 1295, + 1303 + ], + "to_pin": "IOLDO", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=OREG": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 1945, + 1945, + 1945 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "LSR", + "setup": [ + 141, + 141, + 141 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA0", + "setup": [ + 148, + 148, + 148 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 74, + 74, + 74 + ], + "pin": "CE", + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 1945, + 1945, + 1945 + ] + }, + { + "falling": [ + 1200, + 1200, + 1200 + ], + "from_pin": "CLK", + "rising": [ + 1200, + 1200, + 1200 + ], + "to_pin": "IOLDO", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=TSREG": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 1945, + 1945, + 1945 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "LSR", + "setup": [ + 141, + 141, + 141 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TSDATA0", + "setup": [ + 205, + 205, + 205 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 74, + 74, + 74 + ], + "pin": "CE", + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 1945, + 1945, + 1945 + ] + }, + { + "falling": [ + 1031, + 1031, + 1031 + ], + "from_pin": "CLK", + "rising": [ + 1031, + 1031, + 1031 + ], + "to_pin": "IOLTO", + "type": "IOPath" + } + ], "MULT18X18D:REGS=ALL": [ { "clock": [
diff --git a/ECP5/timing/speed_7/cells.json b/ECP5/timing/speed_7/cells.json index b9c105b..e2d1495 100644 --- a/ECP5/timing/speed_7/cells.json +++ b/ECP5/timing/speed_7/cells.json
@@ -13957,6 +13957,665 @@ "type": "IOPath" } ], + "IOLOGIC:MODE=IDDRX1F": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 215, + 215, + 215 + ], + "pin": "DI", + "setup": [ + 353, + 353, + 353 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "falling": [ + 318, + 318, + 318 + ], + "from_pin": "CLK", + "rising": [ + 318, + 318, + 318 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 318, + 318, + 318 + ], + "from_pin": "CLK", + "rising": [ + 318, + 318, + 318 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IDDRX2F": [ + { + "clock": [ + "negedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1524, + 1524, + 1524 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": [ + "posedge", + "ECLK" + ], + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "hold": [ + 55, + 55, + 55 + ], + "pin": "DI", + "setup": [ + 365, + 365, + 365 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1524, + 1524, + 1524 + ] + }, + { + "falling": [ + 403, + 403, + 403 + ], + "from_pin": "CLK", + "rising": [ + 403, + 403, + 403 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 403, + 403, + 403 + ], + "from_pin": "CLK", + "rising": [ + 403, + 403, + 403 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + }, + { + "falling": [ + 403, + 403, + 403 + ], + "from_pin": "CLK", + "rising": [ + 403, + 403, + 403 + ], + "to_pin": "RXDATA2", + "type": "IOPath" + }, + { + "falling": [ + 403, + 403, + 403 + ], + "from_pin": "CLK", + "rising": [ + 403, + 403, + 403 + ], + "to_pin": "RXDATA3", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IREG": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 1648, + 1648, + 1648 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "LSR", + "setup": [ + 105, + 105, + 105 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 285, + 285, + 285 + ], + "pin": "DI", + "setup": [ + 378, + 378, + 378 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 69, + 69, + 69 + ], + "pin": "CE", + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 1648, + 1648, + 1648 + ] + }, + { + "falling": [ + 419, + 419, + 419 + ], + "from_pin": "CLK", + "rising": [ + 419, + 419, + 419 + ], + "to_pin": "INFF", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=ODDRX1F": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "falling": [ + 861, + 863, + 865 + ], + "from_pin": "CLK", + "rising": [ + 861, + 863, + 865 + ], + "to_pin": "IOLDO", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=ODDRX2F": [ + { + "clock": [ + "negedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1425, + 1425, + 1425 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA0", + "setup": [ + 103, + 103, + 103 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA1", + "setup": [ + 103, + 103, + 103 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA2", + "setup": [ + 103, + 103, + 103 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA3", + "setup": [ + 103, + 103, + 103 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": [ + "posedge", + "CLK" + ], + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1425, + 1425, + 1425 + ] + }, + { + "falling": [ + 1131, + 1136, + 1141 + ], + "from_pin": "ECLK", + "rising": [ + 1131, + 1136, + 1141 + ], + "to_pin": "IOLDO", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=OREG": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 1648, + 1648, + 1648 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "LSR", + "setup": [ + 117, + 117, + 117 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TXDATA0", + "setup": [ + 130, + 130, + 130 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 66, + 66, + 66 + ], + "pin": "CE", + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 1648, + 1648, + 1648 + ] + }, + { + "falling": [ + 1109, + 1109, + 1109 + ], + "from_pin": "CLK", + "rising": [ + 1109, + 1109, + 1109 + ], + "to_pin": "IOLDO", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=TSREG": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 1648, + 1648, + 1648 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "LSR", + "setup": [ + 117, + 117, + 117 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "TSDATA0", + "setup": [ + 180, + 180, + 180 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 66, + 66, + 66 + ], + "pin": "CE", + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 1648, + 1648, + 1648 + ] + }, + { + "falling": [ + 898, + 898, + 898 + ], + "from_pin": "CLK", + "rising": [ + 898, + 898, + 898 + ], + "to_pin": "IOLTO", + "type": "IOPath" + } + ], "MULT18X18D:REGS=ALL": [ { "clock": [
diff --git a/ECP5/timing/speed_8/cells.json b/ECP5/timing/speed_8/cells.json index 0c1a1a6..396542d 100644 --- a/ECP5/timing/speed_8/cells.json +++ b/ECP5/timing/speed_8/cells.json
@@ -13957,6 +13957,665 @@ "type": "IOPath" } ], + "IOLOGIC:MODE=IDDRX1F": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 197, + 197, + 197 + ], + "pin": "DI", + "setup": [ + 305, + 305, + 305 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "falling": [ + 281, + 281, + 281 + ], + "from_pin": "CLK", + "rising": [ + 281, + 281, + 281 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 281, + 281, + 281 + ], + "from_pin": "CLK", + "rising": [ + 281, + 281, + 281 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IDDRX2F": [ + { + "clock": [ + "negedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1250, + 1250, + 1250 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": [ + "posedge", + "ECLK" + ], + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "hold": [ + 98, + 98, + 98 + ], + "pin": "DI", + "setup": [ + 284, + 284, + 284 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1250, + 1250, + 1250 + ] + }, + { + "falling": [ + 353, + 353, + 353 + ], + "from_pin": "CLK", + "rising": [ + 353, + 353, + 353 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 353, + 353, + 353 + ], + "from_pin": "CLK", + "rising": [ + 353, + 353, + 353 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + }, + { + "falling": [ + 353, + 353, + 353 + ], + "from_pin": "CLK", + "rising": [ + 353, + 353, + 353 + ], + "to_pin": "RXDATA2", + "type": "IOPath" + }, + { + "falling": [ + 353, + 353, + 353 + ], + "from_pin": "CLK", + "rising": [ + 353, + 353, + 353 + ], + "to_pin": "RXDATA3", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IREG": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 1351, + 1351, + 1351 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": "LSR", + "setup": [ + 81, + 81, + 81 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 258, + 258, + 258 + ], + "pin": "DI", + "setup": [ + 317, + 317, + 317 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 62, + 62, + 62 + ], + "pin": "CE", + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 1351, + 1351, + 1351 + ] + }, + { + "falling": [ + 364, + 364, + 364 + ], + "from_pin": "CLK", + "rising": [ + 364, + 364, + 364 + ], + "to_pin": "INFF", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=ODDRX1F": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 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+ "rising": [ + 763, + 763, + 763 + ], + "to_pin": "IOLTO", + "type": "IOPath" + } + ], "MULT18X18D:REGS=ALL": [ { "clock": [
diff --git a/ECP5/timing/speed_8_5G/cells.json b/ECP5/timing/speed_8_5G/cells.json index a6df9a0..e9194df 100644 --- a/ECP5/timing/speed_8_5G/cells.json +++ b/ECP5/timing/speed_8_5G/cells.json
@@ -13957,6 +13957,665 @@ "type": "IOPath" } ], + "IOLOGIC:MODE=IDDRX1F": [ + { + "clock": [ + "negedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 164, + 164, + 164 + ], + "pin": "DI", + "setup": [ + 254, + 254, + 254 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "CLK" + ], + "type": "Width", + "width": [ + 2000, + 2000, + 2000 + ] + }, + { + "falling": [ + 232, + 232, + 232 + ], + "from_pin": "CLK", + "rising": [ + 232, + 232, + 232 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 232, + 232, + 232 + ], + "from_pin": "CLK", + "rising": [ + 232, + 232, + 232 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IDDRX2F": [ + { + "clock": [ + "negedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1250, + 1250, + 1250 + ] + }, + { + "clock": [ + "posedge", + "CLK" + ], + "hold": [ + 0, + 0, + 0 + ], + "pin": [ + "posedge", + "ECLK" + ], + "setup": [ + 0, + 0, + 0 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "hold": [ + 81, + 81, + 81 + ], + "pin": "DI", + "setup": [ + 236, + 236, + 236 + ], + "type": "SetupHold" + }, + { + "clock": [ + "posedge", + "ECLK" + ], + "type": "Width", + "width": [ + 1250, + 1250, + 1250 + ] + }, + { + "falling": [ + 291, + 291, + 291 + ], + "from_pin": "CLK", + "rising": [ + 291, + 291, + 291 + ], + "to_pin": "RXDATA0", + "type": "IOPath" + }, + { + "falling": [ + 291, + 291, + 291 + ], + "from_pin": "CLK", + "rising": [ + 291, + 291, + 291 + ], + "to_pin": "RXDATA1", + "type": "IOPath" + }, + { + "falling": [ + 291, + 291, + 291 + ], + "from_pin": "CLK", + "rising": [ + 291, + 291, + 291 + ], + "to_pin": "RXDATA2", + "type": "IOPath" + }, + { + "falling": [ + 291, + 291, + 291 + ], + "from_pin": "CLK", + "rising": [ + 291, + 291, + 291 + ], + "to_pin": "RXDATA3", + "type": "IOPath" + } + ], + "IOLOGIC:MODE=IREG": [ + { + "clock": [ + "negedge", + "CLK" + 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"rising": [ + 631, + 631, + 631 + ], + "to_pin": "IOLTO", + "type": "IOPath" + } + ], "MULT18X18D:REGS=ALL": [ { "clock": [