Update to prjtrellis 3e23af2e0dda2294b46bdfee878bbaa6d33271f7

Signed-off-by: David Shah <davey1576@gmail.com>

ECP5/tiledata/EBR_CMUX_LL/bits.db

diff --git a/ECP5/tiledata/EBR_CMUX_LL/bits.db b/ECP5/tiledata/EBR_CMUX_LL/bits.db
index ca41c29..c37c120 100644
--- a/ECP5/tiledata/EBR_CMUX_LL/bits.db
+++ b/ECP5/tiledata/EBR_CMUX_LL/bits.db
@@ -12,6 +12,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_CMUX_LR/bits.db

diff --git a/ECP5/tiledata/EBR_CMUX_LR/bits.db b/ECP5/tiledata/EBR_CMUX_LR/bits.db
index d5c735f..1ed657c 100644
--- a/ECP5/tiledata/EBR_CMUX_LR/bits.db
+++ b/ECP5/tiledata/EBR_CMUX_LR/bits.db
@@ -47,14 +47,16 @@
 CLKB !F104B0
 INV F104B0
 
-.config_enum EBR0.DP16KD.DATA_WIDTH_A 9
-1 F40B0 F47B0 F78B0
-2 F40B0 !F47B0 F78B0
-4 F40B0 !F47B0 !F78B0
-9 !F40B0 !F47B0 !F78B0
+.config_enum EBR0.DP16KD.DATA_WIDTH_A 18
+1 F40B0 F47B0 F51B0 F78B0
+18 !F40B0 !F47B0 !F51B0 !F78B0
+2 F40B0 !F47B0 F51B0 F78B0
+4 F40B0 !F47B0 F51B0 !F78B0
+9 !F40B0 !F47B0 F51B0 !F78B0
 
-.config_enum EBR0.DP16KD.DATA_WIDTH_B 9
+.config_enum EBR0.DP16KD.DATA_WIDTH_B 18
 1 F23B0 F31B0 F32B0
+18 !F23B0 !F31B0 !F32B0
 2 !F23B0 F31B0 F32B0
 4 !F23B0 !F31B0 F32B0
 9 !F23B0 !F31B0 !F32B0

ECP5/tiledata/EBR_CMUX_UL/bits.db

diff --git a/ECP5/tiledata/EBR_CMUX_UL/bits.db b/ECP5/tiledata/EBR_CMUX_UL/bits.db
index ce69675..a1c0749 100644
--- a/ECP5/tiledata/EBR_CMUX_UL/bits.db
+++ b/ECP5/tiledata/EBR_CMUX_UL/bits.db
@@ -12,6 +12,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_CMUX_UR/bits.db

diff --git a/ECP5/tiledata/EBR_CMUX_UR/bits.db b/ECP5/tiledata/EBR_CMUX_UR/bits.db
index d5c735f..1ed657c 100644
--- a/ECP5/tiledata/EBR_CMUX_UR/bits.db
+++ b/ECP5/tiledata/EBR_CMUX_UR/bits.db
@@ -47,14 +47,16 @@
 CLKB !F104B0
 INV F104B0
 
-.config_enum EBR0.DP16KD.DATA_WIDTH_A 9
-1 F40B0 F47B0 F78B0
-2 F40B0 !F47B0 F78B0
-4 F40B0 !F47B0 !F78B0
-9 !F40B0 !F47B0 !F78B0
+.config_enum EBR0.DP16KD.DATA_WIDTH_A 18
+1 F40B0 F47B0 F51B0 F78B0
+18 !F40B0 !F47B0 !F51B0 !F78B0
+2 F40B0 !F47B0 F51B0 F78B0
+4 F40B0 !F47B0 F51B0 !F78B0
+9 !F40B0 !F47B0 F51B0 !F78B0
 
-.config_enum EBR0.DP16KD.DATA_WIDTH_B 9
+.config_enum EBR0.DP16KD.DATA_WIDTH_B 18
 1 F23B0 F31B0 F32B0
+18 !F23B0 !F31B0 !F32B0
 2 !F23B0 F31B0 F32B0
 4 !F23B0 !F31B0 F32B0
 9 !F23B0 !F31B0 !F32B0

ECP5/tiledata/EBR_SPINE_LL0/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_LL0/bits.db b/ECP5/tiledata/EBR_SPINE_LL0/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_LL0/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_LL0/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_LL1/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_LL1/bits.db b/ECP5/tiledata/EBR_SPINE_LL1/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_LL1/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_LL1/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_LL2/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_LL2/bits.db b/ECP5/tiledata/EBR_SPINE_LL2/bits.db
index ca41c29..c37c120 100644
--- a/ECP5/tiledata/EBR_SPINE_LL2/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_LL2/bits.db
@@ -12,6 +12,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_LR0/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_LR0/bits.db b/ECP5/tiledata/EBR_SPINE_LR0/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_LR0/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_LR0/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_LR1/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_LR1/bits.db b/ECP5/tiledata/EBR_SPINE_LR1/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_LR1/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_LR1/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_LR2/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_LR2/bits.db b/ECP5/tiledata/EBR_SPINE_LR2/bits.db
index ca41c29..c37c120 100644
--- a/ECP5/tiledata/EBR_SPINE_LR2/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_LR2/bits.db
@@ -12,6 +12,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_UL0/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_UL0/bits.db b/ECP5/tiledata/EBR_SPINE_UL0/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_UL0/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_UL0/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_UL1/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_UL1/bits.db b/ECP5/tiledata/EBR_SPINE_UL1/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_UL1/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_UL1/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_UL2/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_UL2/bits.db b/ECP5/tiledata/EBR_SPINE_UL2/bits.db
index ca41c29..c37c120 100644
--- a/ECP5/tiledata/EBR_SPINE_UL2/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_UL2/bits.db
@@ -12,6 +12,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_UR0/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_UR0/bits.db b/ECP5/tiledata/EBR_SPINE_UR0/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_UR0/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_UR0/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_UR1/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_UR1/bits.db b/ECP5/tiledata/EBR_SPINE_UR1/bits.db
index a1fc978..9a00f59 100644
--- a/ECP5/tiledata/EBR_SPINE_UR1/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_UR1/bits.db
@@ -60,6 +60,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/EBR_SPINE_UR2/bits.db

diff --git a/ECP5/tiledata/EBR_SPINE_UR2/bits.db b/ECP5/tiledata/EBR_SPINE_UR2/bits.db
index ca41c29..c37c120 100644
--- a/ECP5/tiledata/EBR_SPINE_UR2/bits.db
+++ b/ECP5/tiledata/EBR_SPINE_UR2/bits.db
@@ -12,6 +12,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0

ECP5/tiledata/MIB_EBR0/bits.db

diff --git a/ECP5/tiledata/MIB_EBR0/bits.db b/ECP5/tiledata/MIB_EBR0/bits.db
index d5c735f..1ed657c 100644
--- a/ECP5/tiledata/MIB_EBR0/bits.db
+++ b/ECP5/tiledata/MIB_EBR0/bits.db
@@ -47,14 +47,16 @@
 CLKB !F104B0
 INV F104B0
 
-.config_enum EBR0.DP16KD.DATA_WIDTH_A 9
-1 F40B0 F47B0 F78B0
-2 F40B0 !F47B0 F78B0
-4 F40B0 !F47B0 !F78B0
-9 !F40B0 !F47B0 !F78B0
+.config_enum EBR0.DP16KD.DATA_WIDTH_A 18
+1 F40B0 F47B0 F51B0 F78B0
+18 !F40B0 !F47B0 !F51B0 !F78B0
+2 F40B0 !F47B0 F51B0 F78B0
+4 F40B0 !F47B0 F51B0 !F78B0
+9 !F40B0 !F47B0 F51B0 !F78B0
 
-.config_enum EBR0.DP16KD.DATA_WIDTH_B 9
+.config_enum EBR0.DP16KD.DATA_WIDTH_B 18
 1 F23B0 F31B0 F32B0
+18 !F23B0 !F31B0 !F32B0
 2 !F23B0 F31B0 F32B0
 4 !F23B0 !F31B0 F32B0
 9 !F23B0 !F31B0 !F32B0

ECP5/tiledata/MIB_EBR1/bits.db

diff --git a/ECP5/tiledata/MIB_EBR1/bits.db b/ECP5/tiledata/MIB_EBR1/bits.db
index a082113..6e24d57 100644
--- a/ECP5/tiledata/MIB_EBR1/bits.db
+++ b/ECP5/tiledata/MIB_EBR1/bits.db
@@ -20,6 +20,13 @@
 ASYNC F20B0
 SYNC !F20B0
 
+.config_enum EBR0.DP16KD.DATA_WIDTH_B 18
+1 F81B0
+18 !F81B0
+2 F81B0
+4 F81B0
+9 F81B0
+
 .config_enum EBR0.GSR ENABLED
 DISABLED F67B0
 ENABLED !F67B0

ECP5/tiledata/MIB_EBR2/bits.db

diff --git a/ECP5/tiledata/MIB_EBR2/bits.db b/ECP5/tiledata/MIB_EBR2/bits.db
index 9092703..01ed0b5 100644
--- a/ECP5/tiledata/MIB_EBR2/bits.db
+++ b/ECP5/tiledata/MIB_EBR2/bits.db
@@ -35,14 +35,16 @@
 CLKA !F47B0
 INV F47B0
 
-.config_enum EBR1.DP16KD.DATA_WIDTH_A 9
-1 F66B0 F74B0 F104B0
-2 F66B0 !F74B0 F104B0
-4 F66B0 !F74B0 !F104B0
-9 !F66B0 !F74B0 !F104B0
+.config_enum EBR1.DP16KD.DATA_WIDTH_A 18
+1 F66B0 F74B0 F78B0 F104B0
+18 !F66B0 !F74B0 !F78B0 !F104B0
+2 F66B0 !F74B0 F78B0 F104B0
+4 F66B0 !F74B0 F78B0 !F104B0
+9 !F66B0 !F74B0 F78B0 !F104B0
 
-.config_enum EBR1.DP16KD.DATA_WIDTH_B 9
+.config_enum EBR1.DP16KD.DATA_WIDTH_B 18
 1 F50B0 F57B0 F58B0
+18 !F50B0 !F57B0 !F58B0
 2 !F50B0 F57B0 F58B0
 4 !F50B0 !F57B0 F58B0
 9 !F50B0 !F57B0 !F58B0

ECP5/tiledata/MIB_EBR4/bits.db

diff --git a/ECP5/tiledata/MIB_EBR4/bits.db b/ECP5/tiledata/MIB_EBR4/bits.db
index a4b6c69..47a7043 100644
--- a/ECP5/tiledata/MIB_EBR4/bits.db
+++ b/ECP5/tiledata/MIB_EBR4/bits.db
@@ -6,6 +6,13 @@
 !F96B0
 !F90B0
 
+.config_enum EBR1.DP16KD.DATA_WIDTH_B 18
+1 F1B0
+18 !F1B0
+2 F1B0
+4 F1B0
+9 F1B0
+
 .config_enum EBR1.PDPW16KD.DATA_WIDTH_R 36
 1 F1B0
 18 !F1B0
@@ -26,14 +33,16 @@
 CLKA !F74B0
 INV F74B0
 
-.config_enum EBR2.DP16KD.DATA_WIDTH_A 9
-1 F93B0 F100B0
-2 F93B0 !F100B0
-4 F93B0 !F100B0
-9 !F93B0 !F100B0
+.config_enum EBR2.DP16KD.DATA_WIDTH_A 18
+1 F93B0 F100B0 F104B0
+18 !F93B0 !F100B0 !F104B0
+2 F93B0 !F100B0 F104B0
+4 F93B0 !F100B0 F104B0
+9 !F93B0 !F100B0 F104B0
 
-.config_enum EBR2.DP16KD.DATA_WIDTH_B 9
+.config_enum EBR2.DP16KD.DATA_WIDTH_B 18
 1 F76B0 F83B0 F85B0
+18 !F76B0 !F83B0 !F85B0
 2 !F76B0 F83B0 F85B0
 4 !F76B0 !F83B0 F85B0
 9 !F76B0 !F83B0 !F85B0

ECP5/tiledata/MIB_EBR5/bits.db

diff --git a/ECP5/tiledata/MIB_EBR5/bits.db b/ECP5/tiledata/MIB_EBR5/bits.db
index d3f2cb2..85f6ad6 100644
--- a/ECP5/tiledata/MIB_EBR5/bits.db
+++ b/ECP5/tiledata/MIB_EBR5/bits.db
@@ -53,8 +53,9 @@
 CLKB !F50B0
 INV F50B0
 
-.config_enum EBR2.DP16KD.DATA_WIDTH_A 9
+.config_enum EBR2.DP16KD.DATA_WIDTH_A 18
 1 F25B0
+18 !F25B0
 2 F25B0
 4 !F25B0
 9 !F25B0

ECP5/tiledata/MIB_EBR6/bits.db

diff --git a/ECP5/tiledata/MIB_EBR6/bits.db b/ECP5/tiledata/MIB_EBR6/bits.db
index 876966e..96e437f 100644
--- a/ECP5/tiledata/MIB_EBR6/bits.db
+++ b/ECP5/tiledata/MIB_EBR6/bits.db
@@ -1,6 +1,13 @@
 # Routing Mux Bits
 
 # Non-Routing Configuration
+.config_enum EBR2.DP16KD.DATA_WIDTH_B 18
+1 F28B0
+18 !F28B0
+2 F28B0
+4 F28B0
+9 F28B0
+
 .config_enum EBR2.GSR ENABLED
 DISABLED F14B0
 ENABLED !F14B0
@@ -30,8 +37,9 @@
 CLKA !F100B0
 INV F100B0
 
-.config_enum EBR3.DP16KD.DATA_WIDTH_B 9
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
 1 F103B0
+18 !F103B0
 2 !F103B0
 4 !F103B0
 9 !F103B0

ECP5/tiledata/MIB_EBR7/bits.db

diff --git a/ECP5/tiledata/MIB_EBR7/bits.db b/ECP5/tiledata/MIB_EBR7/bits.db
index 5044387..546784f 100644
--- a/ECP5/tiledata/MIB_EBR7/bits.db
+++ b/ECP5/tiledata/MIB_EBR7/bits.db
@@ -58,14 +58,16 @@
 CLKB !F77B0
 INV F77B0
 
-.config_enum EBR3.DP16KD.DATA_WIDTH_A 9
-1 F13B0 F20B0 F51B0
-2 F13B0 !F20B0 F51B0
-4 F13B0 !F20B0 !F51B0
-9 !F13B0 !F20B0 !F51B0
+.config_enum EBR3.DP16KD.DATA_WIDTH_A 18
+1 F13B0 F20B0 F24B0 F51B0
+18 !F13B0 !F20B0 !F24B0 !F51B0
+2 F13B0 !F20B0 F24B0 F51B0
+4 F13B0 !F20B0 F24B0 !F51B0
+9 !F13B0 !F20B0 F24B0 !F51B0
 
-.config_enum EBR3.DP16KD.DATA_WIDTH_B 9
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
 1 F3B0 F4B0
+18 !F3B0 !F4B0
 2 F3B0 F4B0
 4 !F3B0 F4B0
 9 !F3B0 !F4B0

ECP5/tiledata/MIB_EBR8/bits.db

diff --git a/ECP5/tiledata/MIB_EBR8/bits.db b/ECP5/tiledata/MIB_EBR8/bits.db
index ca41c29..c37c120 100644
--- a/ECP5/tiledata/MIB_EBR8/bits.db
+++ b/ECP5/tiledata/MIB_EBR8/bits.db
@@ -12,6 +12,13 @@
 -
 -
 
+.config_enum EBR3.DP16KD.DATA_WIDTH_B 18
+1 F55B0
+18 !F55B0
+2 F55B0
+4 F55B0
+9 F55B0
+
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0