| # Routing Mux Bits |
| |
| # Non-Routing Configuration |
| .config DCU.CH0_CC_MATCH_1 0000000000 |
| F48B1 |
| F49B1 |
| F50B1 |
| F51B1 |
| F54B1 |
| F55B1 |
| F56B1 |
| F57B1 |
| F82B1 |
| F83B1 |
| |
| .config DCU.CH0_CC_MATCH_2 0000000000 |
| F58B1 |
| F59B1 |
| F60B1 |
| F61B1 |
| F62B1 |
| F63B1 |
| F64B1 |
| F65B1 |
| F84B1 |
| F85B1 |
| |
| .config DCU.CH0_CC_MATCH_3 0000000000 |
| F66B1 |
| F67B1 |
| F68B1 |
| F69B1 |
| F70B1 |
| F71B1 |
| F72B1 |
| F73B1 |
| F86B1 |
| F87B1 |
| |
| .config DCU.CH0_CC_MATCH_4 0000000000 |
| F74B1 |
| F75B1 |
| F76B1 |
| F77B1 |
| F78B1 |
| F79B1 |
| F80B1 |
| F81B1 |
| F88B1 |
| F89B1 |
| |
| .config DCU.CH0_CTC_BYPASS 0 |
| F36B1 |
| |
| .config DCU.CH0_DEC_BYPASS 0 |
| F35B1 |
| |
| .config DCU.CH0_ENABLE_CG_ALIGN 0 |
| F15B1 |
| |
| .config DCU.CH0_ENC_BYPASS 0 |
| F27B1 |
| |
| .config DCU.CH0_GE_AN_ENABLE 0 |
| F12B1 |
| |
| .config DCU.CH0_INVERT_RX 0 |
| F8B1 |
| |
| .config DCU.CH0_INVERT_TX 0 |
| F9B1 |
| |
| .config DCU.CH0_LSM_DISABLE 0 |
| F39B1 |
| |
| .config DCU.CH0_MATCH_2_ENABLE 0 |
| F44B1 |
| |
| .config DCU.CH0_MATCH_4_ENABLE 0 |
| F45B1 |
| |
| .config DCU.CH0_MIN_IPG_CNT 00 |
| F46B1 |
| F47B1 |
| |
| .config DCU.CH0_PCIE_EI_EN 0 |
| F22B1 |
| |
| .config DCU.CH0_PCIE_MODE 0 |
| F2B1 |
| |
| .config DCU.CH0_PCS_DET_TIME_SEL 00 |
| F20B1 |
| F21B1 |
| |
| .config DCU.CH0_PRBS_ENABLE 0 |
| F14B1 |
| |
| .config DCU.CH0_PRBS_LOCK 0 |
| F13B1 |
| |
| .config DCU.CH0_PRBS_SELECTION 0 |
| F10B1 |
| |
| .config DCU.CH0_RIO_MODE 0 |
| F3B1 |
| |
| .config DCU.CH0_RX_GEAR_BYPASS 0 |
| F37B1 |
| |
| .config DCU.CH0_RX_GEAR_MODE 0 |
| F19B1 |
| |
| .config DCU.CH0_RX_SB_BYPASS 0 |
| F33B1 |
| |
| .config DCU.CH0_SB_BYPASS 0 |
| F30B1 |
| |
| .config DCU.CH0_TX_GEAR_BYPASS 0 |
| F25B1 |
| |
| .config DCU.CH0_TX_GEAR_MODE 0 |
| F18B1 |
| |
| .config DCU.CH0_UC_MODE 0 |
| F0B1 |
| |
| .config DCU.CH0_UDF_COMMA_A 1100000000 |
| F98B1 |
| F99B1 |
| F100B1 |
| F101B1 |
| F102B1 |
| F103B1 |
| F104B1 |
| F105B1 |
| - |
| - |
| |
| .config DCU.CH0_UDF_COMMA_MASK 1100000000 |
| F90B1 |
| F91B1 |
| F92B1 |
| F93B1 |
| F94B1 |
| F95B1 |
| F96B1 |
| F97B1 |
| - |
| - |
| |
| .config DCU.CH0_WA_BYPASS 0 |
| F34B1 |
| |
| .config DCU.CH0_WA_MODE 0 |
| F4B1 |
| |
| |
| # Fixed Connections |
| .fixed_conn CH0_RX_REFCLK_DCU CH0_RX_REFCLK |
| |
| .fixed_conn CH1_RX_REFCLK_DCU CH1_RX_REFCLK |
| |
| .fixed_conn D_REFCLKI JTXREFCLK |
| |
| .fixed_conn D_REFCLKI_DCU D_REFCLKI |
| |
| .fixed_conn E27_JD_SYNC_ND_DCU JD_SYNC_PULSE2ND_DCU |
| |
| .fixed_conn E27_JD_TXBIT_CLKN_FROM_ND_DCU JD_TXBIT_CLKN_TO_ND_DCU |
| |
| .fixed_conn E27_JD_TXBIT_CLKP_FROM_ND_DCU JD_TXBIT_CLKP_TO_ND_DCU |
| |
| .fixed_conn E27_JD_TXPLL_LOL_FROM_ND_DCU JD_TXPLL_LOL_TO_ND_DCU |
| |
| .fixed_conn E27_JREFCLKFROMND JTXREFCLK |
| |
| .fixed_conn EXTREFCLK JREFCLKO_EXTREF |
| |
| .fixed_conn G_JPCSARXCLK0 JCH0_FF_RX_PCLK_DCU |
| |
| .fixed_conn G_JPCSARXCLK1 JCH1_FF_RX_PCLK_DCU |
| |
| .fixed_conn G_JPCSATXCLK0 JCH0_FF_TX_PCLK_DCU |
| |
| .fixed_conn G_JPCSATXCLK1 JCH1_FF_TX_PCLK_DCU |
| |
| .fixed_conn JCH0RXREFCLKCIB N1E4_JCLK0 |
| |
| .fixed_conn JCH0_FFC_CDR_EN_BITSLIP_DCU N1E1_JA1 |
| |
| .fixed_conn JCH0_FFC_DIV11_MODE_RX_DCU N1E1_JC0 |
| |
| .fixed_conn JCH0_FFC_DIV11_MODE_TX_DCU N1_JD2 |
| |
| .fixed_conn JCH0_FFC_EI_EN_DCU N1_JB5 |
| |
| .fixed_conn JCH0_FFC_ENABLE_CGALIGN_DCU N1_JC0 |
| |
| .fixed_conn JCH0_FFC_FB_LOOPBACK_DCU N1_JC2 |
| |
| .fixed_conn JCH0_FFC_LANE_RX_RST_DCU N1E1_JA5 |
| |
| .fixed_conn JCH0_FFC_LANE_TX_RST_DCU N1_JC4 |
| |
| .fixed_conn JCH0_FFC_LDR_CORE2TX_EN_DCU N1_JA5 |
| |
| .fixed_conn JCH0_FFC_PCIE_CT_DCU N1_JD4 |
| |
| .fixed_conn JCH0_FFC_PCIE_DET_EN_DCU N1_JB3 |
| |
| .fixed_conn JCH0_FFC_PFIFO_CLR_DCU N1E1_JC4 |
| |
| .fixed_conn JCH0_FFC_RATE_MODE_RX_DCU N1_JA7 |
| |
| .fixed_conn JCH0_FFC_RATE_MODE_TX_DCU N1_JD6 |
| |
| .fixed_conn JCH0_FFC_RRST_DCU N1E1_JA3 |
| |
| .fixed_conn JCH0_FFC_RXPWDNB_DCU N1_JA1 |
| |
| .fixed_conn JCH0_FFC_RX_GEAR_MODE_DCU N1E2_JA5 |
| |
| .fixed_conn JCH0_FFC_SB_INV_RX_DCU N1E1_JC2 |
| |
| .fixed_conn JCH0_FFC_SB_PFIFO_LP_DCU N1_JA3 |
| |
| .fixed_conn JCH0_FFC_SIGNAL_DETECT_DCU N1E1_JA7 |
| |
| .fixed_conn JCH0_FFC_TXPWDNB_DCU N1_JB1 |
| |
| .fixed_conn JCH0_FFC_TX_GEAR_MODE_DCU N1_JC6 |
| |
| .fixed_conn JCH0_FF_EBRD_CLK_DCU N1_JCLK0 |
| |
| .fixed_conn JCH0_FF_RXI_CLK_DCU N1E3_JCLK0 |
| |
| .fixed_conn JCH0_FF_TXI_CLK_DCU N1_JCLK1 |
| |
| .fixed_conn JCH0_FF_TX_D_0_DCU N1E1_JD0 |
| |
| .fixed_conn JCH0_FF_TX_D_10_DCU N1E2_JD2 |
| |
| .fixed_conn JCH0_FF_TX_D_11_DCU N1E2_JB3 |
| |
| .fixed_conn JCH0_FF_TX_D_12_DCU N1E2_JD4 |
| |
| .fixed_conn JCH0_FF_TX_D_13_DCU N1E2_JB5 |
| |
| .fixed_conn JCH0_FF_TX_D_14_DCU N1E2_JD6 |
| |
| .fixed_conn JCH0_FF_TX_D_15_DCU N1E2_JB7 |
| |
| .fixed_conn JCH0_FF_TX_D_16_DCU N1E3_JD0 |
| |
| .fixed_conn JCH0_FF_TX_D_17_DCU N1E3_JB1 |
| |
| .fixed_conn JCH0_FF_TX_D_18_DCU N1E3_JD2 |
| |
| .fixed_conn JCH0_FF_TX_D_19_DCU N1E3_JB3 |
| |
| .fixed_conn JCH0_FF_TX_D_1_DCU N1E1_JB1 |
| |
| .fixed_conn JCH0_FF_TX_D_20_DCU N1E3_JD4 |
| |
| .fixed_conn JCH0_FF_TX_D_21_DCU N1E3_JB5 |
| |
| .fixed_conn JCH0_FF_TX_D_22_DCU N1E3_JD6 |
| |
| .fixed_conn JCH0_FF_TX_D_23_DCU N1E3_JB7 |
| |
| .fixed_conn JCH0_FF_TX_D_2_DCU N1E1_JD2 |
| |
| .fixed_conn JCH0_FF_TX_D_3_DCU N1E1_JB3 |
| |
| .fixed_conn JCH0_FF_TX_D_4_DCU N1E1_JD4 |
| |
| .fixed_conn JCH0_FF_TX_D_5_DCU N1E1_JB5 |
| |
| .fixed_conn JCH0_FF_TX_D_6_DCU N1E1_JD6 |
| |
| .fixed_conn JCH0_FF_TX_D_7_DCU N1E1_JB7 |
| |
| .fixed_conn JCH0_FF_TX_D_8_DCU N1E2_JD0 |
| |
| .fixed_conn JCH0_FF_TX_D_9_DCU N1E2_JB1 |
| |
| .fixed_conn JCH0_HDINN_DCU JINPUT_IN0_APIO |
| |
| .fixed_conn JCH0_HDINP_DCU JINPUT_IP0_APIO |
| |
| .fixed_conn JCH0_LDR_CORE2TX_DCU N1_JB7 |
| |
| .fixed_conn JCH0_SCIEN_DCU N1E2_JC6 |
| |
| .fixed_conn JCH0_SCISEL_DCU N1E2_JA7 |
| |
| .fixed_conn JCH1RXREFCLKCIB N1E6_JCLK1 |
| |
| .fixed_conn JCH1_FFC_CDR_EN_BITSLIP_DCU N1E5_JA3 |
| |
| .fixed_conn JCH1_FFC_DIV11_MODE_RX_DCU N1E6_JD0 |
| |
| .fixed_conn JCH1_FFC_DIV11_MODE_TX_DCU N1E7_JD6 |
| |
| .fixed_conn JCH1_FFC_EI_EN_DCU N1E7_JB3 |
| |
| .fixed_conn JCH1_FFC_ENABLE_CGALIGN_DCU N1E6_JB7 |
| |
| .fixed_conn JCH1_FFC_FB_LOOPBACK_DCU N1E6_JB5 |
| |
| .fixed_conn JCH1_FFC_LANE_RX_RST_DCU N1E6_JD2 |
| |
| .fixed_conn JCH1_FFC_LANE_TX_RST_DCU N1E7_JD0 |
| |
| .fixed_conn JCH1_FFC_LDR_CORE2TX_EN_DCU N1E6_JA7 |
| |
| .fixed_conn JCH1_FFC_PCIE_CT_DCU N1E7_JD4 |
| |
| .fixed_conn JCH1_FFC_PCIE_DET_EN_DCU N1E7_JB5 |
| |
| .fixed_conn JCH1_FFC_PFIFO_CLR_DCU N1E6_JB3 |
| |
| .fixed_conn JCH1_FFC_RATE_MODE_RX_DCU N1E6_JC4 |
| |
| .fixed_conn JCH1_FFC_RATE_MODE_TX_DCU N1E7_JD2 |
| |
| .fixed_conn JCH1_FFC_RRST_DCU N1E6_JC0 |
| |
| .fixed_conn JCH1_FFC_RXPWDNB_DCU N1E6_JD6 |
| |
| .fixed_conn JCH1_FFC_RX_GEAR_MODE_DCU N1E5_JA1 |
| |
| .fixed_conn JCH1_FFC_SB_INV_RX_DCU N1E5_JC2 |
| |
| .fixed_conn JCH1_FFC_SB_PFIFO_LP_DCU N1E6_JD4 |
| |
| .fixed_conn JCH1_FFC_SIGNAL_DETECT_DCU N1E6_JB1 |
| |
| .fixed_conn JCH1_FFC_TXPWDNB_DCU N1E7_JB7 |
| |
| .fixed_conn JCH1_FFC_TX_GEAR_MODE_DCU N1E6_JC6 |
| |
| .fixed_conn JCH1_FF_EBRD_CLK_DCU N1E7_JCLK0 |
| |
| .fixed_conn JCH1_FF_RXI_CLK_DCU N1E6_JCLK0 |
| |
| .fixed_conn JCH1_FF_TXI_CLK_DCU N1E7_JCLK1 |
| |
| .fixed_conn JCH1_FF_TX_D_0_DCU N1E8_JD0 |
| |
| .fixed_conn JCH1_FF_TX_D_10_DCU N1E9_JD2 |
| |
| .fixed_conn JCH1_FF_TX_D_11_DCU N1E9_JB3 |
| |
| .fixed_conn JCH1_FF_TX_D_12_DCU N1E9_JD4 |
| |
| .fixed_conn JCH1_FF_TX_D_13_DCU N1E9_JB5 |
| |
| .fixed_conn JCH1_FF_TX_D_14_DCU N1E9_JD6 |
| |
| .fixed_conn JCH1_FF_TX_D_15_DCU N1E9_JB7 |
| |
| .fixed_conn JCH1_FF_TX_D_16_DCU N1E10_JD0 |
| |
| .fixed_conn JCH1_FF_TX_D_17_DCU N1E10_JB1 |
| |
| .fixed_conn JCH1_FF_TX_D_18_DCU N1E10_JD2 |
| |
| .fixed_conn JCH1_FF_TX_D_19_DCU N1E10_JB3 |
| |
| .fixed_conn JCH1_FF_TX_D_1_DCU N1E8_JB1 |
| |
| .fixed_conn JCH1_FF_TX_D_20_DCU N1E10_JD4 |
| |
| .fixed_conn JCH1_FF_TX_D_21_DCU N1E10_JB5 |
| |
| .fixed_conn JCH1_FF_TX_D_22_DCU N1E10_JD6 |
| |
| .fixed_conn JCH1_FF_TX_D_23_DCU N1E10_JB7 |
| |
| .fixed_conn JCH1_FF_TX_D_2_DCU N1E8_JD2 |
| |
| .fixed_conn JCH1_FF_TX_D_3_DCU N1E8_JB3 |
| |
| .fixed_conn JCH1_FF_TX_D_4_DCU N1E8_JD4 |
| |
| .fixed_conn JCH1_FF_TX_D_5_DCU N1E8_JB5 |
| |
| .fixed_conn JCH1_FF_TX_D_6_DCU N1E8_JD6 |
| |
| .fixed_conn JCH1_FF_TX_D_7_DCU N1E8_JB7 |
| |
| .fixed_conn JCH1_FF_TX_D_8_DCU N1E9_JD0 |
| |
| .fixed_conn JCH1_FF_TX_D_9_DCU N1E9_JB1 |
| |
| .fixed_conn JCH1_HDINN_DCU JINPUT_IN1_APIO |
| |
| .fixed_conn JCH1_HDINP_DCU JINPUT_IP1_APIO |
| |
| .fixed_conn JCH1_LDR_CORE2TX_DCU N1E7_JB1 |
| |
| .fixed_conn JCH1_SCIEN_DCU N1E3_JC2 |
| |
| .fixed_conn JCH1_SCISEL_DCU N1E3_JA3 |
| |
| .fixed_conn JD_CIN0_DCU N1E5_JD2 |
| |
| .fixed_conn JD_CIN10_DCU N1E5_JB1 |
| |
| .fixed_conn JD_CIN11_DCU N1E5_JD0 |
| |
| .fixed_conn JD_CIN1_DCU N1E5_JB3 |
| |
| .fixed_conn JD_CIN2_DCU N1E5_JD4 |
| |
| .fixed_conn JD_CIN3_DCU N1E5_JB5 |
| |
| .fixed_conn JD_CIN4_DCU N1E5_JD6 |
| |
| .fixed_conn JD_CIN5_DCU N1E5_JB7 |
| |
| .fixed_conn JD_CIN6_DCU N1E5_JC4 |
| |
| .fixed_conn JD_CIN7_DCU N1E5_JA5 |
| |
| .fixed_conn JD_CIN8_DCU N1E5_JC6 |
| |
| .fixed_conn JD_CIN9_DCU N1E5_JA7 |
| |
| .fixed_conn JD_CYAWSTN_DCU N1E3_JC0 |
| |
| .fixed_conn JD_FFC_DUAL_RST_DCU N1E4_JC2 |
| |
| .fixed_conn JD_FFC_MACROPDB_DCU N1E11_JD2 |
| |
| .fixed_conn JD_FFC_MACRO_RST_DCU N1E11_JB1 |
| |
| .fixed_conn JD_FFC_SYNC_TOGGLE_DCU N1E11_JB5 |
| |
| .fixed_conn JD_FFC_TRST_DCU N1E11_JB3 |
| |
| .fixed_conn JD_SCAN_ENABLE_DCU N1E4_JA7 |
| |
| .fixed_conn JD_SCAN_IN_0_DCU N1E11_JD0 |
| |
| .fixed_conn JD_SCAN_IN_1_DCU N1E6_JA5 |
| |
| .fixed_conn JD_SCAN_IN_2_DCU N1E5_JC0 |
| |
| .fixed_conn JD_SCAN_IN_3_DCU N1E2_JC4 |
| |
| .fixed_conn JD_SCAN_IN_4_DCU N1E1_JC6 |
| |
| .fixed_conn JD_SCAN_IN_5_DCU N1_JD0 |
| |
| .fixed_conn JD_SCAN_IN_6_DCU N1E3_JC6 |
| |
| .fixed_conn JD_SCAN_IN_7_DCU N1E3_JA7 |
| |
| .fixed_conn JD_SCAN_MODE_DCU N1E4_JC0 |
| |
| .fixed_conn JD_SCAN_RESET_DCU N1E4_JA1 |
| |
| .fixed_conn JD_SCIADDR0_DCU N1E2_JC0 |
| |
| .fixed_conn JD_SCIADDR1_DCU N1E2_JA1 |
| |
| .fixed_conn JD_SCIADDR2_DCU N1E2_JC2 |
| |
| .fixed_conn JD_SCIADDR3_DCU N1E2_JA3 |
| |
| .fixed_conn JD_SCIADDR4_DCU N1E3_JC4 |
| |
| .fixed_conn JD_SCIADDR5_DCU N1E3_JA5 |
| |
| .fixed_conn JD_SCIENAUX_DCU N1E4_JA5 |
| |
| .fixed_conn JD_SCIRD_DCU N1E4_JC6 |
| |
| .fixed_conn JD_SCISELAUX_DCU N1E4_JC4 |
| |
| .fixed_conn JD_SCIWDATA0_DCU N1E4_JD0 |
| |
| .fixed_conn JD_SCIWDATA1_DCU N1E4_JB1 |
| |
| .fixed_conn JD_SCIWDATA2_DCU N1E4_JD2 |
| |
| .fixed_conn JD_SCIWDATA3_DCU N1E4_JB3 |
| |
| .fixed_conn JD_SCIWDATA4_DCU N1E4_JD4 |
| |
| .fixed_conn JD_SCIWDATA5_DCU N1E4_JB5 |
| |
| .fixed_conn JD_SCIWDATA6_DCU N1E4_JD6 |
| |
| .fixed_conn JD_SCIWDATA7_DCU N1E4_JB7 |
| |
| .fixed_conn JD_SCIWSTN_DCU N1E3_JA1 |
| |
| .fixed_conn JOUTPUT_ON0_APIO JCH0_HDOUTN_DCU |
| |
| .fixed_conn JOUTPUT_ON1_APIO JCH1_HDOUTN_DCU |
| |
| .fixed_conn JOUTPUT_OP0_APIO JCH0_HDOUTP_DCU |
| |
| .fixed_conn JOUTPUT_OP1_APIO JCH1_HDOUTP_DCU |
| |
| .fixed_conn JTXREFCLK EXTREFCLK |
| |
| .fixed_conn JTXREFCLK KEEPWIRE |
| |
| .fixed_conn JTXREFCLKCIB N1E11_JCLK0 |
| |
| .fixed_conn N1E10_JF0 JCH1_FF_RX_D_16_DCU |
| |
| .fixed_conn N1E10_JF1 JCH1_FF_RX_D_17_DCU |
| |
| .fixed_conn N1E10_JF2 JCH1_FF_RX_D_18_DCU |
| |
| .fixed_conn N1E10_JF3 JCH1_FF_RX_D_19_DCU |
| |
| .fixed_conn N1E10_JF4 JCH1_FF_RX_D_20_DCU |
| |
| .fixed_conn N1E10_JF5 JCH1_FF_RX_D_21_DCU |
| |
| .fixed_conn N1E10_JF6 JCH1_FF_RX_D_22_DCU |
| |
| .fixed_conn N1E10_JF7 JCH1_FF_RX_D_23_DCU |
| |
| .fixed_conn N1E10_JQ0 JCH1_FFS_SKP_DELETED_DCU |
| |
| .fixed_conn N1E10_JQ1 JCH1_FFS_SKP_ADDED_DCU |
| |
| .fixed_conn N1E11_JF0 JCH1_LDR_RX2CORE_DCU |
| |
| .fixed_conn N1E11_JF1 JD_SCAN_OUT_7_DCU |
| |
| .fixed_conn N1E11_JF2 JCH1_FFS_TXFBFIFO_ERROR_DCU |
| |
| .fixed_conn N1E11_JF3 JCH1_FFS_PCIE_CON_DCU |
| |
| .fixed_conn N1E11_JF4 JCH1_FFS_PCIE_DONE_DCU |
| |
| .fixed_conn N1E11_JF5 JD_SCAN_OUT_3_DCU |
| |
| .fixed_conn N1E11_JF6 JD_COUT1_DCU |
| |
| .fixed_conn N1E11_JF7 JD_SCAN_OUT_0_DCU |
| |
| .fixed_conn N1E11_JQ0 JD_FFS_PLOL_DCU |
| |
| .fixed_conn N1E1_JF0 JCH0_FF_RX_D_0_DCU |
| |
| .fixed_conn N1E1_JF1 JCH0_FF_RX_D_1_DCU |
| |
| .fixed_conn N1E1_JF2 JCH0_FF_RX_D_2_DCU |
| |
| .fixed_conn N1E1_JF3 JCH0_FF_RX_D_3_DCU |
| |
| .fixed_conn N1E1_JF4 JCH0_FF_RX_D_4_DCU |
| |
| .fixed_conn N1E1_JF5 JCH0_FF_RX_D_5_DCU |
| |
| .fixed_conn N1E1_JF6 JCH0_FF_RX_D_6_DCU |
| |
| .fixed_conn N1E1_JF7 JCH0_FF_RX_D_7_DCU |
| |
| .fixed_conn N1E1_JQ0 JCH0_FFS_CC_OVERRUN_DCU |
| |
| .fixed_conn N1E1_JQ1 JCH0_FFS_RLOL_DCU |
| |
| .fixed_conn N1E2_JF0 JCH0_FF_RX_D_8_DCU |
| |
| .fixed_conn N1E2_JF1 JCH0_FF_RX_D_9_DCU |
| |
| .fixed_conn N1E2_JF2 JCH0_FF_RX_D_10_DCU |
| |
| .fixed_conn N1E2_JF3 JCH0_FF_RX_D_11_DCU |
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| .fixed_conn N1E2_JF4 JCH0_FF_RX_D_12_DCU |
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| .fixed_conn N1E2_JF5 JCH0_FF_RX_D_13_DCU |
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| .fixed_conn N1E2_JF6 JCH0_FF_RX_D_14_DCU |
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| .fixed_conn N1E2_JF7 JCH0_FF_RX_D_15_DCU |
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| .fixed_conn N1E2_JQ0 JCH0_FFS_RLOS_DCU |
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| .fixed_conn N1E2_JQ1 JCH0_FFS_LS_SYNC_STATUS_DCU |
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| .fixed_conn N1E3_JF0 JCH0_FF_RX_D_16_DCU |
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| .fixed_conn N1E3_JF1 JCH0_FF_RX_D_17_DCU |
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| .fixed_conn N1E3_JF2 JCH0_FF_RX_D_18_DCU |
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| .fixed_conn N1E3_JF3 JCH0_FF_RX_D_19_DCU |
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| .fixed_conn N1E3_JF4 JCH0_FF_RX_D_20_DCU |
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| .fixed_conn N1E3_JF5 JCH0_FF_RX_D_21_DCU |
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| .fixed_conn N1E3_JF6 JCH0_FF_RX_D_22_DCU |
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| .fixed_conn N1E3_JF7 JCH0_FF_RX_D_23_DCU |
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| .fixed_conn N1E3_JQ0 JCH0_FF_RX_F_CLK_DCU |
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| .fixed_conn N1E3_JQ1 JCH0_FF_RX_H_CLK_DCU |
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| .fixed_conn N1E4_JF1 JD_COUT19_DCU |
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| .fixed_conn N1E4_JF2 JD_COUT16_DCU |
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| .fixed_conn N1E4_JF3 JD_COUT6_DCU |
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| .fixed_conn N1E4_JF4 JD_COUT7_DCU |
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| .fixed_conn N1E4_JF5 JD_COUT8_DCU |
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| .fixed_conn N1E4_JF6 JD_COUT9_DCU |
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| .fixed_conn N1E4_JF7 JD_COUT10_DCU |
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| .fixed_conn N1E4_JQ0 JD_COUT17_DCU |
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| .fixed_conn N1E4_JQ1 JD_COUT18_DCU |
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| .fixed_conn N1E4_JQ4 JCH0_FFS_CC_UNDERRUN_DCU |
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| .fixed_conn N1E4_JQ5 JCH0_FFS_RXFBFIFO_ERROR_DCU |
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| .fixed_conn N1E5_JF0 JD_COUT11_DCU |
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| .fixed_conn N1E5_JF1 JD_COUT12_DCU |
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| .fixed_conn N1E5_JF2 JD_COUT13_DCU |
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| .fixed_conn N1E5_JF3 JD_COUT14_DCU |
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| .fixed_conn N1E5_JF4 JD_COUT15_DCU |
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| .fixed_conn N1E5_JF5 JD_COUT0_DCU |
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| .fixed_conn N1E5_JF6 JD_COUT2_DCU |
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| .fixed_conn N1E5_JF7 JD_COUT3_DCU |
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| .fixed_conn N1E5_JQ0 JD_COUT4_DCU |
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| .fixed_conn N1E5_JQ1 JD_COUT5_DCU |
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| .fixed_conn N1E5_JQ4 JD_SCAN_OUT_6_DCU |
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| .fixed_conn N1E5_JQ5 JD_SCIINT_DCU |
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| .fixed_conn N1E6_JF0 JD_SCIRDATA0_DCU |
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| .fixed_conn N1E6_JF1 JD_SCIRDATA1_DCU |
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| .fixed_conn N1E6_JF2 JD_SCIRDATA2_DCU |
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| .fixed_conn N1E6_JF3 JD_SCIRDATA3_DCU |
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| .fixed_conn N1E6_JF4 JD_SCIRDATA4_DCU |
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| .fixed_conn N1E6_JF5 JD_SCIRDATA5_DCU |
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| .fixed_conn N1E6_JF6 JD_SCIRDATA6_DCU |
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| .fixed_conn N1E6_JF7 JD_SCIRDATA7_DCU |
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| .fixed_conn N1E6_JQ0 JCH1_FF_RX_F_CLK_DCU |
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| .fixed_conn N1E6_JQ1 JCH1_FF_RX_H_CLK_DCU |
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| .fixed_conn N1E7_JF1 JCH1_FFS_RXFBFIFO_ERROR_DCU |
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| .fixed_conn N1E7_JF2 JCH1_FFS_CC_UNDERRUN_DCU |
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| .fixed_conn N1E7_JF3 JCH1_FFS_LS_SYNC_STATUS_DCU |
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| .fixed_conn N1E7_JF4 JCH1_FFS_RLOS_DCU |
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| .fixed_conn N1E7_JF5 JCH1_FFS_RLOL_DCU |
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| .fixed_conn N1E7_JF6 JCH1_FFS_CC_OVERRUN_DCU |
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| .fixed_conn N1E7_JF7 JD_SCAN_OUT_4_DCU |
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| .fixed_conn N1E7_JQ0 JCH1_FF_TX_F_CLK_DCU |
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| .fixed_conn N1E7_JQ1 JCH1_FF_TX_H_CLK_DCU |
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| .fixed_conn N1E8_JF0 JCH1_FF_RX_D_0_DCU |
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| .fixed_conn N1E8_JF1 JCH1_FF_RX_D_1_DCU |
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| .fixed_conn N1E8_JF2 JCH1_FF_RX_D_2_DCU |
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| .fixed_conn N1E8_JF3 JCH1_FF_RX_D_3_DCU |
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| .fixed_conn N1E8_JF4 JCH1_FF_RX_D_4_DCU |
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| .fixed_conn N1E8_JF5 JCH1_FF_RX_D_5_DCU |
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| .fixed_conn N1E8_JF6 JCH1_FF_RX_D_6_DCU |
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| .fixed_conn N1E8_JF7 JCH1_FF_RX_D_7_DCU |
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| .fixed_conn N1E9_JF0 JCH1_FF_RX_D_8_DCU |
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| .fixed_conn N1E9_JF1 JCH1_FF_RX_D_9_DCU |
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| .fixed_conn N1E9_JF2 JCH1_FF_RX_D_10_DCU |
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| .fixed_conn N1E9_JF3 JCH1_FF_RX_D_11_DCU |
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| .fixed_conn N1E9_JF4 JCH1_FF_RX_D_12_DCU |
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| .fixed_conn N1E9_JF5 JCH1_FF_RX_D_13_DCU |
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| .fixed_conn N1E9_JF6 JCH1_FF_RX_D_14_DCU |
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| .fixed_conn N1E9_JF7 JCH1_FF_RX_D_15_DCU |
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| .fixed_conn N1_JF0 JD_SCAN_OUT_1_DCU |
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| .fixed_conn N1_JF1 JCH0_FFS_PCIE_DONE_DCU |
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| .fixed_conn N1_JF2 JCH0_FFS_PCIE_CON_DCU |
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| .fixed_conn N1_JF3 JD_SCAN_OUT_2_DCU |
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| .fixed_conn N1_JF4 JCH0_FFS_TXFBFIFO_ERROR_DCU |
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| .fixed_conn N1_JF5 JD_SCAN_OUT_5_DCU |
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| .fixed_conn N1_JF6 JCH0_LDR_RX2CORE_DCU |
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| .fixed_conn N1_JF7 JCH0_FFS_SKP_ADDED_DCU |
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| .fixed_conn N1_JQ0 JCH0_FF_TX_H_CLK_DCU |
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| .fixed_conn N1_JQ1 JCH0_FF_TX_F_CLK_DCU |
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| .fixed_conn N1_JQ4 JCH0_FFS_SKP_DELETED_DCU |
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| .fixed_conn REFCLKN_EXTREF INPUT_REFN_APIO |
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| .fixed_conn REFCLKP_EXTREF INPUT_REFP_APIO |
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| .fixed_conn RXREFCLK0 EXTREFCLK |
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| .fixed_conn RXREFCLK0 KEEPWIRE |
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| .fixed_conn RXREFCLK1 EXTREFCLK |
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| .fixed_conn RXREFCLK1 KEEPWIRE |
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