Update to prjtrellis 911d4536a22f26f34691284fb8bf6fd81acab43f Signed-off-by: David Shah <dave@ds0.me>

diff --git a/ECP5/tiledata/BANKREF8/bits.db b/ECP5/tiledata/BANKREF8/bits.db
index bc5ef05..e28a263 100644
--- a/ECP5/tiledata/BANKREF8/bits.db
+++ b/ECP5/tiledata/BANKREF8/bits.db

@@ -86,7 +86,7 @@
 NONE !F3B0 !F16B0 F17B0 !F18B0
 
 .config_enum CLKOP_ENABLE DISABLED
-DISABLED !F77B0
+DISABLED -
 ENABLED F77B0
 
 .config_enum CLKOP_TRIM_DELAY 0
@@ -100,15 +100,15 @@
 RISING F95B0
 
 .config_enum CLKOS2_ENABLE DISABLED
-DISABLED !F79B0
+DISABLED -
 ENABLED F79B0
 
 .config_enum CLKOS3_ENABLE DISABLED
-DISABLED !F80B0
+DISABLED -
 ENABLED F80B0
 
 .config_enum CLKOS_ENABLE DISABLED
-DISABLED !F78B0
+DISABLED -
 ENABLED F78B0
 
 .config_enum CLKOS_TRIM_DELAY 0
@@ -126,19 +126,19 @@
 ENABLED F82B0
 
 .config_enum OUTDIVIDER_MUXA DIVA
-DIVA !F73B0
+DIVA -
 REFCLK F73B0
 
 .config_enum OUTDIVIDER_MUXB DIVB
-DIVB !F74B0
+DIVB -
 REFCLK F74B0
 
 .config_enum OUTDIVIDER_MUXC DIVC
-DIVC !F75B0
+DIVC -
 REFCLK F75B0
 
 .config_enum OUTDIVIDER_MUXD DIVD
-DIVD !F76B0
+DIVD -
 REFCLK F76B0
 
 .config_enum SYNC_ENABLE DISABLED

diff --git a/ECP5/tiledata/PLL0_LL/bits.db b/ECP5/tiledata/PLL0_LL/bits.db
index 18e5ad9..4c0b772 100644
--- a/ECP5/tiledata/PLL0_LL/bits.db
+++ b/ECP5/tiledata/PLL0_LL/bits.db

@@ -196,7 +196,7 @@
 
 .config_enum MODE NONE
 EHXPLLL F0B0
-NONE !F0B0
+NONE -
 
 .config_enum PLLRST_ENA DISABLED
 DISABLED !F2B0

diff --git a/ECP5/tiledata/PLL0_LR/bits.db b/ECP5/tiledata/PLL0_LR/bits.db
index cd9b831..7a6ca21 100644
--- a/ECP5/tiledata/PLL0_LR/bits.db
+++ b/ECP5/tiledata/PLL0_LR/bits.db

@@ -196,7 +196,7 @@
 
 .config_enum MODE NONE
 EHXPLLL F0B0
-NONE !F0B0
+NONE -
 
 .config_enum PLLRST_ENA DISABLED
 DISABLED !F2B0

diff --git a/ECP5/tiledata/PLL0_UL/bits.db b/ECP5/tiledata/PLL0_UL/bits.db
index 40c79a2..3c4fc54 100644
--- a/ECP5/tiledata/PLL0_UL/bits.db
+++ b/ECP5/tiledata/PLL0_UL/bits.db

@@ -202,7 +202,7 @@
 
 .config_enum MODE NONE
 EHXPLLL F0B0
-NONE !F0B0
+NONE -
 
 .config_enum PLLRST_ENA DISABLED
 DISABLED !F2B0

diff --git a/ECP5/tiledata/PLL0_UR/bits.db b/ECP5/tiledata/PLL0_UR/bits.db
index 389074a..5e650dd 100644
--- a/ECP5/tiledata/PLL0_UR/bits.db
+++ b/ECP5/tiledata/PLL0_UR/bits.db

@@ -202,7 +202,7 @@
 
 .config_enum MODE NONE
 EHXPLLL F9B0
-NONE !F9B0
+NONE -
 
 .config_enum PLLRST_ENA DISABLED
 DISABLED !F7B0

diff --git a/ECP5/tiledata/PLL1_LR/bits.db b/ECP5/tiledata/PLL1_LR/bits.db
index 6f9bdb9..4f5a17d 100644
--- a/ECP5/tiledata/PLL1_LR/bits.db
+++ b/ECP5/tiledata/PLL1_LR/bits.db

@@ -78,7 +78,7 @@
 F85B0
 
 .config_enum CLKOP_ENABLE DISABLED
-DISABLED !F77B0
+DISABLED -
 ENABLED F77B0
 
 .config_enum CLKOP_TRIM_DELAY 0
@@ -92,15 +92,15 @@
 RISING F95B0
 
 .config_enum CLKOS2_ENABLE DISABLED
-DISABLED !F79B0
+DISABLED -
 ENABLED F79B0
 
 .config_enum CLKOS3_ENABLE DISABLED
-DISABLED !F80B0
+DISABLED -
 ENABLED F80B0
 
 .config_enum CLKOS_ENABLE DISABLED
-DISABLED !F78B0
+DISABLED -
 ENABLED F78B0
 
 .config_enum CLKOS_TRIM_DELAY 0
@@ -118,19 +118,19 @@
 ENABLED F82B0
 
 .config_enum OUTDIVIDER_MUXA DIVA
-DIVA !F73B0
+DIVA -
 REFCLK F73B0
 
 .config_enum OUTDIVIDER_MUXB DIVB
-DIVB !F74B0
+DIVB -
 REFCLK F74B0
 
 .config_enum OUTDIVIDER_MUXC DIVC
-DIVC !F75B0
+DIVC -
 REFCLK F75B0
 
 .config_enum OUTDIVIDER_MUXD DIVD
-DIVD !F76B0
+DIVD -
 REFCLK F76B0
 
 .config_enum SYNC_ENABLE DISABLED

diff --git a/ECP5/tiledata/PLL1_UL/bits.db b/ECP5/tiledata/PLL1_UL/bits.db
index 8bd4d22..6eeda8f 100644
--- a/ECP5/tiledata/PLL1_UL/bits.db
+++ b/ECP5/tiledata/PLL1_UL/bits.db

@@ -78,7 +78,7 @@
 F5B8
 
 .config_enum CLKOP_ENABLE DISABLED
-DISABLED !F7B7
+DISABLED -
 ENABLED F7B7
 
 .config_enum CLKOP_TRIM_DELAY 0
@@ -92,15 +92,15 @@
 RISING F5B9
 
 .config_enum CLKOS2_ENABLE DISABLED
-DISABLED !F9B7
+DISABLED -
 ENABLED F9B7
 
 .config_enum CLKOS3_ENABLE DISABLED
-DISABLED !F0B8
+DISABLED -
 ENABLED F0B8
 
 .config_enum CLKOS_ENABLE DISABLED
-DISABLED !F8B7
+DISABLED -
 ENABLED F8B7
 
 .config_enum CLKOS_TRIM_DELAY 0
@@ -118,19 +118,19 @@
 ENABLED F2B8
 
 .config_enum OUTDIVIDER_MUXA DIVA
-DIVA !F3B7
+DIVA -
 REFCLK F3B7
 
 .config_enum OUTDIVIDER_MUXB DIVB
-DIVB !F4B7
+DIVB -
 REFCLK F4B7
 
 .config_enum OUTDIVIDER_MUXC DIVC
-DIVC !F5B7
+DIVC -
 REFCLK F5B7
 
 .config_enum OUTDIVIDER_MUXD DIVD
-DIVD !F6B7
+DIVD -
 REFCLK F6B7
 
 .config_enum SYNC_ENABLE DISABLED

diff --git a/ECP5/tiledata/PLL1_UR/bits.db b/ECP5/tiledata/PLL1_UR/bits.db
index 58ace5e..0faa1bd 100644
--- a/ECP5/tiledata/PLL1_UR/bits.db
+++ b/ECP5/tiledata/PLL1_UR/bits.db

@@ -78,7 +78,7 @@
 F4B8
 
 .config_enum CLKOP_ENABLE DISABLED
-DISABLED !F2B7
+DISABLED -
 ENABLED F2B7
 
 .config_enum CLKOP_TRIM_DELAY 0
@@ -92,15 +92,15 @@
 RISING F4B9
 
 .config_enum CLKOS2_ENABLE DISABLED
-DISABLED !F0B7
+DISABLED -
 ENABLED F0B7
 
 .config_enum CLKOS3_ENABLE DISABLED
-DISABLED !F9B8
+DISABLED -
 ENABLED F9B8
 
 .config_enum CLKOS_ENABLE DISABLED
-DISABLED !F1B7
+DISABLED -
 ENABLED F1B7
 
 .config_enum CLKOS_TRIM_DELAY 0
@@ -118,19 +118,19 @@
 ENABLED F7B8
 
 .config_enum OUTDIVIDER_MUXA DIVA
-DIVA !F6B7
+DIVA -
 REFCLK F6B7
 
 .config_enum OUTDIVIDER_MUXB DIVB
-DIVB !F5B7
+DIVB -
 REFCLK F5B7
 
 .config_enum OUTDIVIDER_MUXC DIVC
-DIVC !F4B7
+DIVC -
 REFCLK F4B7
 
 .config_enum OUTDIVIDER_MUXD DIVD
-DIVD !F3B7
+DIVD -
 REFCLK F3B7
 
 .config_enum SYNC_ENABLE DISABLED