Adding SPINE bits for all parts Signed-off-by: David Shah <davey1576@gmail.com>
diff --git a/ECP5/tiledata/DSP_SPINE_UL0/bits.db b/ECP5/tiledata/DSP_SPINE_UL0/bits.db index 8b13789..177222e 100644 --- a/ECP5/tiledata/DSP_SPINE_UL0/bits.db +++ b/ECP5/tiledata/DSP_SPINE_UL0/bits.db
@@ -1 +1,53 @@ +# Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + + +# Non-Routing Configuration + +# Fixed Connections
diff --git a/ECP5/tiledata/DSP_SPINE_UL1/bits.db b/ECP5/tiledata/DSP_SPINE_UL1/bits.db index 8b13789..177222e 100644 --- a/ECP5/tiledata/DSP_SPINE_UL1/bits.db +++ b/ECP5/tiledata/DSP_SPINE_UL1/bits.db
@@ -1 +1,53 @@ +# Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + + +# Non-Routing Configuration + +# Fixed Connections
diff --git a/ECP5/tiledata/DSP_SPINE_UR0/bits.db b/ECP5/tiledata/DSP_SPINE_UR0/bits.db index 8b13789..177222e 100644 --- a/ECP5/tiledata/DSP_SPINE_UR0/bits.db +++ b/ECP5/tiledata/DSP_SPINE_UR0/bits.db
@@ -1 +1,53 @@ +# Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + + +# Non-Routing Configuration + +# Fixed Connections
diff --git a/ECP5/tiledata/DSP_SPINE_UR1/bits.db b/ECP5/tiledata/DSP_SPINE_UR1/bits.db index 8b13789..177222e 100644 --- a/ECP5/tiledata/DSP_SPINE_UR1/bits.db +++ b/ECP5/tiledata/DSP_SPINE_UR1/bits.db
@@ -1 +1,53 @@ +# Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + + +# Non-Routing Configuration + +# Fixed Connections
diff --git a/ECP5/tiledata/EBR_SPINE_LL2/bits.db b/ECP5/tiledata/EBR_SPINE_LL2/bits.db index c37c120..9a00f59 100644 --- a/ECP5/tiledata/EBR_SPINE_LL2/bits.db +++ b/ECP5/tiledata/EBR_SPINE_LL2/bits.db
@@ -1,4 +1,52 @@ # Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 + +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + # Non-Routing Configuration .config EBR3.WID 111100000
diff --git a/ECP5/tiledata/EBR_SPINE_LL3/bits.db b/ECP5/tiledata/EBR_SPINE_LL3/bits.db index 8b13789..177222e 100644 --- a/ECP5/tiledata/EBR_SPINE_LL3/bits.db +++ b/ECP5/tiledata/EBR_SPINE_LL3/bits.db
@@ -1 +1,53 @@ +# Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + + +# Non-Routing Configuration + +# Fixed Connections
diff --git a/ECP5/tiledata/EBR_SPINE_LR2/bits.db b/ECP5/tiledata/EBR_SPINE_LR2/bits.db index c37c120..9a00f59 100644 --- a/ECP5/tiledata/EBR_SPINE_LR2/bits.db +++ b/ECP5/tiledata/EBR_SPINE_LR2/bits.db
@@ -1,4 +1,52 @@ # Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 + +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + # Non-Routing Configuration .config EBR3.WID 111100000
diff --git a/ECP5/tiledata/EBR_SPINE_UL2/bits.db b/ECP5/tiledata/EBR_SPINE_UL2/bits.db index c37c120..9a00f59 100644 --- a/ECP5/tiledata/EBR_SPINE_UL2/bits.db +++ b/ECP5/tiledata/EBR_SPINE_UL2/bits.db
@@ -1,4 +1,52 @@ # Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 + +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + # Non-Routing Configuration .config EBR3.WID 111100000
diff --git a/ECP5/tiledata/EBR_SPINE_UR2/bits.db b/ECP5/tiledata/EBR_SPINE_UR2/bits.db index c37c120..9a00f59 100644 --- a/ECP5/tiledata/EBR_SPINE_UR2/bits.db +++ b/ECP5/tiledata/EBR_SPINE_UR2/bits.db
@@ -1,4 +1,52 @@ # Routing Mux Bits +.mux G_VPTX0000 +G_HPRX0000 F95B0 + +.mux G_VPTX0100 +G_HPRX0100 F94B0 + +.mux G_VPTX0200 +G_HPRX0200 F93B0 + +.mux G_VPTX0300 +G_HPRX0300 F92B0 + +.mux G_VPTX0400 +G_HPRX0400 F91B0 + +.mux G_VPTX0500 +G_HPRX0500 F90B0 + +.mux G_VPTX0600 +G_HPRX0600 F89B0 + +.mux G_VPTX0700 +G_HPRX0700 F88B0 + +.mux G_VPTX0800 +G_HPRX0800 F87B0 + +.mux G_VPTX0900 +G_HPRX0900 F86B0 + +.mux G_VPTX1000 +G_HPRX1000 F85B0 + +.mux G_VPTX1100 +G_HPRX1100 F84B0 + +.mux G_VPTX1200 +G_HPRX1200 F83B0 + +.mux G_VPTX1300 +G_HPRX1300 F82B0 + +.mux G_VPTX1400 +G_HPRX1400 F81B0 + +.mux G_VPTX1500 +G_HPRX1500 F80B0 + # Non-Routing Configuration .config EBR3.WID 111100000