| # Routing Mux Bits |
| .mux N2_ECLKC |
| BNK_ECLK1 F5B1 |
| |
| .mux N2_ECLKD |
| BNK_ECLK1 F3B6 |
| |
| .mux N2_JDIC |
| N2_INDDC_IOLOGIC F1B1 |
| |
| .mux N2_JDID |
| N2_INDDD_IOLOGIC F9B7 |
| |
| |
| # Non-Routing Configuration |
| .config IOLOGICC.DELAY.DEL_VALUE 0000000 |
| F9B1 |
| F0B0 |
| F1B0 |
| F2B0 |
| F3B0 |
| F4B0 |
| F5B0 |
| |
| .config IOLOGICD.DELAY.DEL_VALUE 0000000 |
| F7B6 |
| F8B6 |
| F9B6 |
| F0B5 |
| F1B5 |
| F2B5 |
| F3B5 |
| |
| .config_enum IOLOGICC.CEIMUX CEMUX |
| 1 F9B5 |
| CEMUX - |
| |
| .config_enum IOLOGICC.CEMUX INV |
| CE F6B0 |
| INV - |
| |
| .config_enum IOLOGICC.CEOMUX CEMUX |
| 1 F1B2 |
| CEMUX - |
| |
| .config_enum IOLOGICC.CLKIMUX 0 |
| 0 - |
| CLK F3B1 |
| INV F2B1 F3B1 |
| |
| .config_enum IOLOGICC.CLKOMUX 0 |
| 0 - |
| CLK F0B2 |
| INV F0B2 F9B3 |
| |
| .config_enum IOLOGICC.DELAY.OUTDEL DISABLED |
| DISABLED - |
| ENABLED F8B3 |
| |
| .config_enum IOLOGICC.DELAY.WAIT_FOR_EDGE DISABLED |
| DISABLED - |
| ENABLED F3B2 |
| |
| .config_enum IOLOGICC.FF.INREGMODE FF |
| FF - |
| LATCH F6B2 |
| |
| .config_enum IOLOGICC.FF.REGSET RESET |
| RESET - |
| SET F4B1 |
| |
| .config_enum IOLOGICC.GSR ENABLED |
| DISABLED F7B1 |
| ENABLED - |
| |
| .config_enum IOLOGICC.IDDRXN.MODE NONE |
| IDDR71 F5B7 F6B7 F7B2 F8B2 |
| IDDRX2 F8B2 |
| NONE - |
| |
| .config_enum IOLOGICC.IOLTOMUX TS |
| NONE - |
| TDDR F4B4 |
| TS - |
| |
| .config_enum IOLOGICC.LOADNMUX 1 |
| 1 - |
| LOADN F4B2 |
| |
| .config_enum IOLOGICC.LSRIMUX 0 |
| 0 - |
| LSRMUX F0B1 |
| |
| .config_enum IOLOGICC.LSRMUX INV |
| INV - |
| LSR F5B2 |
| |
| .config_enum IOLOGICC.LSROMUX 0 |
| 0 - |
| LSRMUX F7B3 |
| |
| .config_enum IOLOGICC.MIDDRX.MODE NONE |
| MIDDRX2 F3B10 F8B2 |
| NONE - |
| |
| .config_enum IOLOGICC.MIDDRX_MODDRX.WRCLKMUX NONE |
| DQSW F2B4 |
| DQSW270 F1B4 F2B4 |
| NONE - |
| |
| .config_enum IOLOGICC.MODDRX.MODE NONE |
| MODDRX2 F1B3 |
| MOSHX2 F0B3 F1B4 |
| NONE - |
| |
| .config_enum IOLOGICC.MODE NONE |
| IDDRX1_ODDRX1 F0B4 F1B2 !F6B3 F7B2 F9B5 |
| IDDRXN F0B4 F1B2 !F6B3 F9B5 |
| IREG_OREG F0B4 !F6B3 |
| MIDDRX_MODDRX F0B4 F1B2 F6B3 F9B5 |
| NONE !F6B3 |
| ODDRXN F0B4 F1B2 F2B3 F3B3 !F6B3 F9B5 |
| |
| .config_enum IOLOGICC.MTDDRX.DQSW_INVERT DISABLED |
| DISABLED - |
| ENABLED F9B4 |
| |
| .config_enum IOLOGICC.MTDDRX.MODE NONE |
| MTSHX2 F1B3 |
| NONE - |
| |
| .config_enum IOLOGICC.MTDDRX.REGSET RESET |
| RESET - |
| SET F6B4 |
| |
| .config_enum IOLOGICC.ODDRXN.MODE NONE |
| NONE - |
| ODDR71 F0B3 F0B8 F1B3 F1B4 F7B9 F8B9 F9B9 |
| ODDRX2 F1B3 F1B4 |
| |
| .config_enum IOLOGICC.OUTREG.OUTREGMODE FF |
| FF - |
| LATCH F6B5 |
| |
| .config_enum IOLOGICC.OUTREG.REGSET RESET |
| RESET - |
| SET F2B2 |
| |
| .config_enum IOLOGICC.SRMODE ASYNC |
| ASYNC - |
| LSR_OVER_CE F7B0 |
| |
| .config_enum IOLOGICC.TSREG.OUTREGMODE FF |
| FF - |
| LATCH F7B5 |
| |
| .config_enum IOLOGICC.TSREG.REGSET RESET |
| RESET - |
| SET F6B4 |
| |
| .config_enum IOLOGICD.CEIMUX CEMUX |
| 1 F6B10 |
| CEMUX - |
| |
| .config_enum IOLOGICD.CEMUX INV |
| CE F4B5 |
| INV - |
| |
| .config_enum IOLOGICD.CEOMUX CEMUX |
| 1 F9B8 |
| CEMUX - |
| |
| .config_enum IOLOGICD.CLKIMUX 0 |
| 0 - |
| CLK F1B6 |
| INV F0B6 F1B6 |
| |
| .config_enum IOLOGICD.CLKOMUX 0 |
| 0 - |
| CLK F8B8 |
| INV F7B8 F8B8 |
| |
| .config_enum IOLOGICD.DELAY.OUTDEL DISABLED |
| DISABLED - |
| ENABLED F6B8 |
| |
| .config_enum IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED |
| DISABLED - |
| ENABLED F1B7 |
| |
| .config_enum IOLOGICD.FF.INREGMODE FF |
| FF - |
| LATCH F4B7 |
| |
| .config_enum IOLOGICD.FF.REGSET RESET |
| RESET - |
| SET F2B6 |
| |
| .config_enum IOLOGICD.GSR ENABLED |
| DISABLED F5B6 |
| ENABLED - |
| |
| .config_enum IOLOGICD.IDDRXN.MODE NONE |
| IDDR71 F5B7 F6B7 |
| IDDRX2 F6B7 |
| NONE - |
| |
| .config_enum IOLOGICD.IOLTOMUX TS |
| NONE - |
| TDDR F1B9 |
| TS - |
| |
| .config_enum IOLOGICD.LOADNMUX 1 |
| 1 - |
| LOADN F2B7 |
| |
| .config_enum IOLOGICD.LSRIMUX 0 |
| 0 - |
| LSRMUX F8B7 |
| |
| .config_enum IOLOGICD.LSRMUX INV |
| INV - |
| LSR F3B7 |
| |
| .config_enum IOLOGICD.LSROMUX 0 |
| 0 - |
| LSRMUX F5B8 |
| |
| .config_enum IOLOGICD.MIDDRX.MODE NONE |
| MIDDRX2 F2B10 F6B7 |
| NONE - |
| |
| .config_enum IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE |
| DQSW F9B10 |
| DQSW270 F8B10 F9B10 |
| NONE - |
| |
| .config_enum IOLOGICD.MODDRX.MODE NONE |
| MODDRX2 F8B9 |
| MOSHX2 F7B9 F8B10 |
| NONE - |
| |
| .config_enum IOLOGICD.MODE NONE |
| IDDRX1_ODDRX1 !F4B6 F5B7 F6B10 F7B10 F9B8 |
| IDDRXN !F4B6 F6B10 F7B10 F9B8 |
| IREG_OREG !F4B6 F7B10 |
| MIDDRX_MODDRX F4B6 F6B10 F7B10 F9B8 |
| NONE !F4B6 |
| ODDRXN F0B8 !F4B6 F6B10 F7B10 F9B8 F9B9 |
| |
| .config_enum IOLOGICD.MTDDRX.DQSW_INVERT DISABLED |
| DISABLED - |
| ENABLED F6B9 |
| |
| .config_enum IOLOGICD.MTDDRX.MODE NONE |
| MTSHX2 F8B9 |
| NONE - |
| |
| .config_enum IOLOGICD.MTDDRX.REGSET RESET |
| RESET - |
| SET F3B9 |
| |
| .config_enum IOLOGICD.ODDRXN.MODE NONE |
| NONE - |
| ODDR71 F7B9 F8B9 F8B10 |
| ODDRX2 F8B9 F8B10 |
| |
| .config_enum IOLOGICD.OUTREG.OUTREGMODE FF |
| FF - |
| LATCH F4B10 |
| |
| .config_enum IOLOGICD.OUTREG.REGSET RESET |
| RESET - |
| SET F0B7 |
| |
| .config_enum IOLOGICD.SRMODE ASYNC |
| ASYNC - |
| LSR_OVER_CE F5B5 |
| |
| .config_enum IOLOGICD.TSREG.OUTREGMODE FF |
| FF - |
| LATCH F5B10 |
| |
| .config_enum IOLOGICD.TSREG.REGSET RESET |
| RESET - |
| SET F3B9 |
| |
| .config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D |
| BIDIR_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_HSUL12 F7B4 F8B4 |
| BIDIR_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_LVCMOS12 F7B4 F8B4 |
| BIDIR_LVCMOS15 F7B4 F8B4 |
| BIDIR_LVCMOS18 F7B4 F8B4 |
| BIDIR_LVCMOS25 F7B4 F8B4 |
| BIDIR_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_LVCMOS33 F7B4 F8B4 |
| BIDIR_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_LVTTL33 F7B4 F8B4 |
| BIDIR_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_SSTL135_I F7B4 F8B4 |
| BIDIR_SSTL135_II F7B4 F8B4 |
| BIDIR_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_SSTL15_I F7B4 F8B4 |
| BIDIR_SSTL15_II F7B4 F8B4 |
| BIDIR_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| BIDIR_SSTL18_I F7B4 F8B4 |
| BIDIR_SSTL18_II F7B4 F8B4 |
| INPUT_BLVDS25 - |
| INPUT_HSUL12 - |
| INPUT_HSUL12D - |
| INPUT_LVCMOS12 - |
| INPUT_LVCMOS15 - |
| INPUT_LVCMOS18 - |
| INPUT_LVCMOS18D - |
| INPUT_LVCMOS25 - |
| INPUT_LVCMOS25D - |
| INPUT_LVCMOS33 - |
| INPUT_LVCMOS33D - |
| INPUT_LVDS - |
| INPUT_LVPECL33 - |
| INPUT_LVTTL33 - |
| INPUT_MLVDS25 - |
| INPUT_SLVS - |
| INPUT_SSTL135D_I - |
| INPUT_SSTL135D_II - |
| INPUT_SSTL135_I - |
| INPUT_SSTL135_II - |
| INPUT_SSTL15D_I - |
| INPUT_SSTL15D_II - |
| INPUT_SSTL15_I - |
| INPUT_SSTL15_II - |
| INPUT_SSTL18D_I - |
| INPUT_SSTL18D_II - |
| INPUT_SSTL18_I - |
| INPUT_SSTL18_II - |
| INPUT_SUBLVDS - |
| NONE - |
| OUTPUT_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_HSUL12 F7B4 F8B4 |
| OUTPUT_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_LVCMOS12 F7B4 F8B4 |
| OUTPUT_LVCMOS15 F7B4 F8B4 |
| OUTPUT_LVCMOS18 F7B4 F8B4 |
| OUTPUT_LVCMOS25 F7B4 F8B4 |
| OUTPUT_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_LVCMOS33 F7B4 F8B4 |
| OUTPUT_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_LVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_LVPECL33E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_LVTTL33 F7B4 F8B4 |
| OUTPUT_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_SSTL135_I F7B4 F8B4 |
| OUTPUT_SSTL135_II F7B4 F8B4 |
| OUTPUT_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_SSTL15_I F7B4 F8B4 |
| OUTPUT_SSTL15_II F7B4 F8B4 |
| OUTPUT_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4 |
| OUTPUT_SSTL18_I F7B4 F8B4 |
| OUTPUT_SSTL18_II F7B4 F8B4 |
| |
| .config_enum PIOC.DATAMUX_MDDR PADDO |
| IOLDO F2B3 F3B3 |
| PADDO - |
| |
| .config_enum PIOC.DATAMUX_ODDR PADDO |
| IOLDO F3B3 |
| PADDO - |
| |
| .config_enum PIOC.DATAMUX_OREG PADDO |
| IOLDO F2B3 |
| PADDO - |
| |
| .config_enum PIOC.TRIMUX_TSREG PADDT |
| IOLTO F3B4 |
| PADDT - |
| |
| .config_enum PIOD.BASE_TYPE INPUT_HSUL12 |
| BIDIR_HSUL12 F4B9 F5B9 |
| BIDIR_LVCMOS12 F4B9 F5B9 |
| BIDIR_LVCMOS15 F4B9 F5B9 |
| BIDIR_LVCMOS18 F4B9 F5B9 |
| BIDIR_LVCMOS25 F4B9 F5B9 |
| BIDIR_LVCMOS33 F4B9 F5B9 |
| BIDIR_LVTTL33 F4B9 F5B9 |
| BIDIR_SSTL135_I F4B9 F5B9 |
| BIDIR_SSTL135_II F4B9 F5B9 |
| BIDIR_SSTL15_I F4B9 F5B9 |
| BIDIR_SSTL15_II F4B9 F5B9 |
| BIDIR_SSTL18_I F4B9 F5B9 |
| BIDIR_SSTL18_II F4B9 F5B9 |
| INPUT_HSUL12 - |
| INPUT_LVCMOS12 - |
| INPUT_LVCMOS15 - |
| INPUT_LVCMOS18 - |
| INPUT_LVCMOS25 - |
| INPUT_LVCMOS33 - |
| INPUT_LVTTL33 - |
| INPUT_SSTL135_I - |
| INPUT_SSTL135_II - |
| INPUT_SSTL15_I - |
| INPUT_SSTL15_II - |
| INPUT_SSTL18_I - |
| INPUT_SSTL18_II - |
| NONE - |
| OUTPUT_HSUL12 F4B9 F5B9 |
| OUTPUT_LVCMOS12 F4B9 F5B9 |
| OUTPUT_LVCMOS15 F4B9 F5B9 |
| OUTPUT_LVCMOS18 F4B9 F5B9 |
| OUTPUT_LVCMOS25 F4B9 F5B9 |
| OUTPUT_LVCMOS33 F4B9 F5B9 |
| OUTPUT_LVTTL33 F4B9 F5B9 |
| OUTPUT_SSTL135_I F4B9 F5B9 |
| OUTPUT_SSTL135_II F4B9 F5B9 |
| OUTPUT_SSTL15_I F4B9 F5B9 |
| OUTPUT_SSTL15_II F4B9 F5B9 |
| OUTPUT_SSTL18_I F4B9 F5B9 |
| OUTPUT_SSTL18_II F4B9 F5B9 |
| |
| .config_enum PIOD.DATAMUX_MDDR PADDO |
| IOLDO F0B8 F9B9 |
| PADDO - |
| |
| .config_enum PIOD.DATAMUX_ODDR PADDO |
| IOLDO F0B8 |
| PADDO - |
| |
| .config_enum PIOD.DATAMUX_OREG PADDO |
| IOLDO F9B9 |
| PADDO - |
| |
| .config_enum PIOD.TRIMUX_TSREG PADDT |
| IOLTO F0B9 |
| PADDT - |
| |
| |
| # Fixed Connections |
