| # Routing Mux Bits |
| .mux N1W1_JDIB |
| N1W1_INDDB_SIOLOGIC F21B0 |
| |
| |
| # Non-Routing Configuration |
| .config_enum IOLOGICB.CLKIMUX CLK |
| CLK - |
| INV F20B0 |
| |
| .config_enum IOLOGICB.CLKOMUX CLK |
| CLK - |
| INV F43B0 |
| |
| .config_enum IOLOGICB.GSR ENABLED |
| DISABLED F12B0 |
| ENABLED - |
| |
| .config_enum IOLOGICB.LSRIMUX 0 |
| 0 - |
| LSRMUX F22B0 |
| |
| .config_enum IOLOGICB.LSRMUX INV |
| INV - |
| LSR F32B0 |
| |
| .config_enum IOLOGICB.LSROMUX 0 |
| 0 - |
| LSRMUX F45B0 |
| |
| .config_enum IOLOGICB.MODE NONE |
| IDDRX1_ODDRX1 F19B0 F26B0 F41B0 F42B0 F64B0 |
| IREG_OREG F19B0 F42B0 |
| NONE - |
| |
| .config_enum PIOB.BASE_TYPE INPUT_LVCMOS12 |
| BIDIR_LVCMOS12 F54B0 F55B0 |
| BIDIR_LVCMOS15 F54B0 F55B0 |
| BIDIR_LVCMOS18 F54B0 F55B0 |
| BIDIR_LVCMOS25 F54B0 F55B0 |
| BIDIR_LVCMOS33 F54B0 F55B0 |
| BIDIR_LVTTL33 F54B0 F55B0 |
| INPUT_LVCMOS12 - |
| INPUT_LVCMOS15 - |
| INPUT_LVCMOS18 - |
| INPUT_LVCMOS25 - |
| INPUT_LVCMOS33 - |
| INPUT_LVTTL33 - |
| NONE - |
| OUTPUT_LVCMOS12 F54B0 F55B0 |
| OUTPUT_LVCMOS15 F54B0 F55B0 |
| OUTPUT_LVCMOS18 F54B0 F55B0 |
| OUTPUT_LVCMOS25 F54B0 F55B0 |
| OUTPUT_LVCMOS33 F54B0 F55B0 |
| OUTPUT_LVTTL33 F54B0 F55B0 |
| |
| |
| # Fixed Connections |
| .fixed_conn E1_HL7W0001 E1_JF3 |
| |
| .fixed_conn HL7W0001 JF3 |
| |
