| # Routing Mux Bits |
| .mux W1_CLKFB |
| W1_CLKINTFB - |
| W1_JCLKFB1 F8B1 |
| W1_JCLKFB2 F7B1 |
| W1_JCLKFB3 F7B1 F8B1 |
| |
| .mux W1_JCLKOP_PLL |
| W1_CLKI_PLL F9B0 |
| |
| .mux W1_JCLKOS2_PLL |
| W1_CLKI_PLL F9B0 |
| |
| .mux W1_JCLKOS3_PLL |
| W1_CLKI_PLL F9B0 |
| |
| .mux W1_JCLKOS_PLL |
| W1_CLKI_PLL F9B0 |
| |
| .mux W1_REFCLK0 |
| W1_JREFCLK0_0 - |
| W1_JREFCLK0_1 F4B0 |
| W1_JREFCLK0_2 F3B0 |
| W1_JREFCLK0_3 F3B0 F4B0 |
| W1_JREFCLK0_4 F2B0 |
| W1_JREFCLK0_5 F2B0 F4B0 |
| W1_JREFCLK0_6 F2B0 F3B0 |
| |
| .mux W1_REFCLK1 |
| W1_JREFCLK1_0 - |
| W1_JREFCLK1_1 F1B0 |
| W1_JREFCLK1_2 F0B0 |
| W1_JREFCLK1_3 F0B0 F1B0 |
| W1_JREFCLK1_4 F9B1 |
| W1_JREFCLK1_5 F1B0 F9B1 |
| W1_JREFCLK1_6 F0B0 F9B1 |
| |
| |
| # Non-Routing Configuration |
| .config CLKFB_DIV 0000000 |
| F5B2 |
| F4B2 |
| F3B2 |
| F2B2 |
| F1B2 |
| F0B2 |
| F9B3 |
| |
| .config CLKI_DIV 0000000 |
| F2B1 |
| F1B1 |
| F0B1 |
| F9B2 |
| F8B2 |
| F7B2 |
| F6B2 |
| |
| .config CLKOP_CPHASE 0000000 |
| F2B8 |
| F1B8 |
| F0B8 |
| F9B9 |
| F8B9 |
| F7B9 |
| F6B9 |
| |
| .config CLKOP_FPHASE 000 |
| F4B7 |
| F3B7 |
| F2B7 |
| |
| .config CLKOS2_CPHASE 1111110 |
| F8B10 |
| - |
| - |
| - |
| - |
| - |
| - |
| |
| .config CLKOS2_FPHASE 000 |
| F8B8 |
| F7B8 |
| F6B8 |
| |
| .config CLKOS3_FPHASE 000 |
| F5B8 |
| F4B8 |
| F3B8 |
| |
| .config CLKOS_CPHASE 0000000 |
| F5B9 |
| F4B9 |
| F3B9 |
| F2B9 |
| F1B9 |
| F0B9 |
| F9B10 |
| |
| .config CLKOS_FPHASE 000 |
| F1B7 |
| F0B7 |
| F9B8 |
| |
| .config FREQ_LOCK_ACCURACY 00 |
| F4B3 |
| F3B3 |
| |
| .config ICP_CURRENT 00000 |
| F3B4 |
| F2B4 |
| F1B4 |
| F0B4 |
| F9B5 |
| |
| .config KVCO 000 |
| F8B5 |
| F5B5 |
| F4B5 |
| |
| .config LPF_CAPACITOR 00 |
| F5B4 |
| F4B4 |
| |
| .config LPF_RESISTOR 0000000 |
| F2B3 |
| F1B3 |
| F0B3 |
| F9B4 |
| F8B4 |
| F7B4 |
| F6B4 |
| |
| .config MFG_ENABLE_FILTEROPAMP 0 |
| F5B7 |
| |
| .config MFG_EN_UP 0 |
| F9B7 |
| |
| .config MFG_FLOAT_ICP 0 |
| F1B6 |
| |
| .config MFG_FORCE_VFILTER 0 |
| F0B6 |
| |
| .config MFG_GMCREF_SEL 00 |
| F7B7 |
| F6B7 |
| |
| .config MFG_GMC_GAIN 000 |
| F3B5 |
| F2B5 |
| F1B5 |
| |
| .config MFG_GMC_PRESET 0 |
| F6B6 |
| |
| .config MFG_GMC_RESET 0 |
| F5B6 |
| |
| .config MFG_GMC_TEST 0000 |
| F0B5 |
| F9B6 |
| F8B6 |
| F7B6 |
| |
| .config MFG_ICP_TEST 0 |
| F8B7 |
| |
| .config MFG_LF_PRESET 0 |
| F4B6 |
| |
| .config MFG_LF_RESET 0 |
| F3B6 |
| |
| .config MFG_LF_RESGRND 0 |
| F2B6 |
| |
| .config PLL_LOCK_MODE 000 |
| F7B3 |
| F6B3 |
| F5B3 |
| |
| .config_enum FEEDBK_PATH USERCLOCK |
| CLKOP - |
| CLKOS - |
| CLKOS2 - |
| CLKOS3 - |
| INT_OP F5B1 F6B1 F7B1 |
| INT_OS F4B1 F5B1 F6B1 F8B1 |
| INT_OS2 F3B1 F5B1 F6B1 |
| INT_OS3 F3B1 F4B1 F5B1 F7B1 F8B1 |
| USERCLOCK - |
| |
| .config_enum INTFB_WAKE DISABLED |
| DISABLED !F5B0 |
| ENABLED F5B0 |
| |
| .config_enum INT_LOCK_STICKY DISABLED |
| DISABLED !F8B3 |
| ENABLED F8B3 |
| |
| .config_enum MODE NONE |
| EHXPLLL F9B0 |
| NONE - |
| |
| .config_enum PLLRST_ENA DISABLED |
| DISABLED !F7B0 |
| ENABLED F7B0 |
| |
| .config_enum REFIN_RESET DISABLED |
| DISABLED !F8B0 |
| ENABLED F8B0 |
| |
| .config_enum STDBY_ENABLE DISABLED |
| DISABLED !F6B0 |
| ENABLED F6B0 |
| |
| |
| # Fixed Connections |
| .fixed_conn G_JURCPLL0CLKOP W1_JCLKOP_PLL |
| |
| .fixed_conn G_JURCPLL0CLKOS W1_JCLKOS_PLL |
| |
| .fixed_conn G_JURCPLL0CLKOS2 W1_JCLKOS2_PLL |
| |
| .fixed_conn G_JURCPLL0CLKOS3 W1_JCLKOS3_PLL |
| |
| .fixed_conn W1_CLK0_PLLREFCS W1_REFCLK0 |
| |
| .fixed_conn W1_CLK1_PLLREFCS W1_REFCLK1 |
| |
| .fixed_conn W1_CLKFB_PLL W1_CLKFB |
| |
| .fixed_conn W1_CLKINTFB W1_CLKINTFB_PLL |
| |
| .fixed_conn W1_CLKI_PLL W1_PLLCSOUT_PLLREFCS |
| |
| .fixed_conn W1_JCLKFB1 45K_S30_JECLK0 |
| |
| .fixed_conn W1_JCLKFB1 85K_S42_JECLK0 |
| |
| .fixed_conn W1_JCLKFB2 45K_S30_JECLK1 |
| |
| .fixed_conn W1_JCLKFB2 85K_S42_JECLK1 |
| |
| .fixed_conn W1_JCLKFB3 S1W1_JCLK0 |
| |
| .fixed_conn W1_JENCLKOP_PLL W1_JD2 |
| |
| .fixed_conn W1_JENCLKOS2_PLL W1_JB3 |
| |
| .fixed_conn W1_JENCLKOS3_PLL W1_JC3 |
| |
| .fixed_conn W1_JENCLKOS_PLL W1_JA3 |
| |
| .fixed_conn W1_JF0 W1_JCLKOP_PLL |
| |
| .fixed_conn W1_JF2 W1_JCLKOS_PLL |
| |
| .fixed_conn W1_JF4 W1_JCLKOS2_PLL |
| |
| .fixed_conn W1_JF6 W1_JCLKOS3_PLL |
| |
| .fixed_conn W1_JPHASEDIR_PLL W1_JD4 |
| |
| .fixed_conn W1_JPHASELOADREG_PLL W1_JD3 |
| |
| .fixed_conn W1_JPHASESEL0_PLL W1_JB4 |
| |
| .fixed_conn W1_JPHASESEL1_PLL W1_JA4 |
| |
| .fixed_conn W1_JPHASESTEP_PLL W1_JC4 |
| |
| .fixed_conn W1_JPLLWAKESYNC_PLL W1_JC2 |
| |
| .fixed_conn W1_JQ0 W1_JREFCLK_PLL |
| |
| .fixed_conn W1_JQ2 W1_JLOCK_PLL |
| |
| .fixed_conn W1_JQ4 W1_JINTLOCK_PLL |
| |
| .fixed_conn W1_JREFCLK0_0 W1_JCLK0 |
| |
| .fixed_conn W1_JREFCLK0_1 45K_S28_JPADDIC_PIO |
| |
| .fixed_conn W1_JREFCLK0_1 85K_S40_JPADDIC_PIO |
| |
| .fixed_conn W1_JREFCLK0_2 45K_S28_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_2 85K_S40_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_3 45K_S7_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_3 85K_S7_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_4 45K_N4W5_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_4 85K_N4W5_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_5 45K_N4W48_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_5 85K_N4W57_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_6 45K_N4W46_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK0_6 85K_N4W55_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_0 W1_JCLK1 |
| |
| .fixed_conn W1_JREFCLK1_1 45K_S28_JPADDIC_PIO |
| |
| .fixed_conn W1_JREFCLK1_1 85K_S40_JPADDIC_PIO |
| |
| .fixed_conn W1_JREFCLK1_2 45K_S28_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_2 85K_S40_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_3 45K_S7_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_3 85K_S7_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_4 45K_N4W5_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_4 85K_N4W5_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_5 45K_N4W48_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_5 85K_N4W57_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_6 45K_N4W46_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK1_6 85K_N4W55_JPADDIA_PIO |
| |
| .fixed_conn W1_JREFCLK_PLL W1_CLKI_PLL |
| |
| .fixed_conn W1_JRST_PLL W1_JB1 |
| |
| .fixed_conn W1_JSEL_PLLREFCS W1_JB2 |
| |
| .fixed_conn W1_JSTDBY_PLL W1_JLSR0 |
| |
