Update to prjtrellis bc9c16581ad23d82cd6f29b461a669cf213b8a4d Signed-off-by: David Shah <davey1576@gmail.com>
diff --git a/ECP5/tiledata/MIB2_DSP0/bits.db b/ECP5/tiledata/MIB2_DSP0/bits.db index 3772e77..f78f5d5 100644 --- a/ECP5/tiledata/MIB2_DSP0/bits.db +++ b/ECP5/tiledata/MIB2_DSP0/bits.db
@@ -259,5 +259,44 @@ CLK3 - NONE F27B1 F28B1 F79B1 F83B1 +.config_enum MULT18_1.REG_INPUTA_CE CE3 +CE0 F4B1 F5B1 F17B1 F18B1 F23B1 F24B1 F25B1 F29B1 F41B1 F42B1 +CE1 F5B1 F18B1 F24B1 F29B1 F42B1 +CE2 F4B1 F17B1 F23B1 F25B1 F41B1 +CE3 - + +.config_enum MULT18_1.REG_INPUTB_CE CE3 +CE0 F15B1 F16B1 F19B1 F20B1 F43B1 F44B1 +CE1 F16B1 F20B1 F44B1 +CE2 F15B1 F19B1 F43B1 +CE3 - + +.config_enum MULT18_1.REG_INPUTC_CLK NONE +CLK0 F21B1 F22B1 +CLK1 F21B1 F22B1 +CLK2 F21B1 F22B1 +CLK3 F21B1 F22B1 +NONE - + +.config_enum MULT18_1.REG_OUTPUT_CLK NONE +CLK0 F34B1 F35B1 F36B1 F37B1 +CLK1 F34B1 F35B1 F36B1 F37B1 +CLK2 F34B1 F35B1 F36B1 F37B1 +CLK3 F34B1 F35B1 F36B1 F37B1 +NONE - + +.config_enum MULT18_1.REG_PIPELINE_CE CE3 +CE0 F30B1 F31B1 F32B1 F33B1 F45B1 F46B1 F47B1 F48B1 +CE1 F31B1 F33B1 F46B1 F48B1 +CE2 F30B1 F32B1 F45B1 F47B1 +CE3 - + +.config_enum MULT18_1.REG_PIPELINE_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F86B1 F88B1 + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP1/bits.db b/ECP5/tiledata/MIB2_DSP1/bits.db index 32dafda..df36eab 100644 --- a/ECP5/tiledata/MIB2_DSP1/bits.db +++ b/ECP5/tiledata/MIB2_DSP1/bits.db
@@ -251,5 +251,32 @@ ASYNC F40B1 F50B1 F61B1 F70B1 F82B1 F102B1 SYNC - +.config_enum MULT18_1.MODE NONE +MULT18X18D F72B0 F90B0 F101B0 +NONE - + +.config_enum MULT18_1.REG_INPUTA_RST RST3 +RST0 F32B1 F33B1 F68B1 F69B1 F99B1 F100B1 +RST1 F33B1 F69B1 F100B1 +RST2 F32B1 F68B1 F99B1 +RST3 - + +.config_enum MULT18_1.REG_INPUTB_RST RST3 +RST0 F58B1 F59B1 F80B1 F81B1 +RST1 F59B1 F81B1 +RST2 F58B1 F80B1 +RST3 - + +.config_enum MULT18_1.REG_INPUTC_CLK NONE +CLK0 F98B1 F101B1 +CLK1 F98B1 F101B1 +CLK2 F98B1 F101B1 +CLK3 F98B1 F101B1 +NONE - + +.config_enum MULT18_1.RESETMODE SYNC +ASYNC F41B1 F51B1 F60B1 F71B1 F83B1 F103B1 +SYNC - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP2/bits.db b/ECP5/tiledata/MIB2_DSP2/bits.db index f75f79a..3d1ed75 100644 --- a/ECP5/tiledata/MIB2_DSP2/bits.db +++ b/ECP5/tiledata/MIB2_DSP2/bits.db
@@ -214,5 +214,59 @@ ASYNC F4B1 F18B1 F28B1 F40B1 F50B1 F54B1 F64B1 F89B1 F96B1 SYNC - +.config_enum MULT18_1.MODE NONE +MULT18X18D F1B0 F14B0 F82B0 F83B0 F86B0 +NONE - + +.config_enum MULT18_1.REG_INPUTA_CLK CLK3 +CLK0 F102B1 F103B1 +CLK1 F102B1 +CLK2 F103B1 +CLK3 - +NONE - + +.config_enum MULT18_1.REG_INPUTA_RST RST3 +RST0 F2B1 F3B1 F62B1 F63B1 +RST1 F3B1 F63B1 +RST2 F2B1 F62B1 +RST3 - + +.config_enum MULT18_1.REG_INPUTB_CLK CLK3 +CLK0 F100B1 F101B1 +CLK1 F100B1 +CLK2 F101B1 +CLK3 - +NONE - + +.config_enum MULT18_1.REG_INPUTB_RST RST3 +RST0 F68B1 F69B1 +RST1 F69B1 +RST2 F68B1 +RST3 - + +.config_enum MULT18_1.REG_OUTPUT_CLK NONE +CLK0 F48B1 F49B1 F58B1 F59B1 +CLK1 F48B1 F49B1 F58B1 F59B1 +CLK2 F48B1 F49B1 F58B1 F59B1 +CLK3 F48B1 F49B1 F58B1 F59B1 +NONE - + +.config_enum MULT18_1.REG_PIPELINE_CLK CLK3 +CLK0 F87B1 F88B1 F90B1 F91B1 +CLK1 F87B1 F90B1 +CLK2 F88B1 F91B1 +CLK3 - +NONE - + +.config_enum MULT18_1.REG_PIPELINE_RST RST3 +RST0 F26B1 F27B1 F38B1 F39B1 F84B1 F85B1 F94B1 F95B1 +RST1 F27B1 F39B1 F85B1 F95B1 +RST2 F26B1 F38B1 F84B1 F94B1 +RST3 - + +.config_enum MULT18_1.RESETMODE SYNC +ASYNC F5B1 F19B1 F29B1 F41B1 F51B1 F55B1 F65B1 F77B1 F86B1 +SYNC - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP3/bits.db b/ECP5/tiledata/MIB2_DSP3/bits.db index 6ac38f1..717e509 100644 --- a/ECP5/tiledata/MIB2_DSP3/bits.db +++ b/ECP5/tiledata/MIB2_DSP3/bits.db
@@ -458,5 +458,48 @@ MULT18X18D F30B0 F34B1 NONE - +.config_enum MULT18_1.MODE NONE +MULT18X18D F28B1 F30B0 +NONE - + +.config_enum MULT18_1.REG_INPUTA_CLK CLK3 +CLK0 F20B1 F21B1 F24B1 F25B1 F36B1 F37B1 F48B1 F49B1 +CLK1 F20B1 F24B1 F36B1 F48B1 +CLK2 F21B1 F25B1 F37B1 F49B1 +CLK3 - +NONE - + +.config_enum MULT18_1.REG_INPUTB_CLK CLK3 +CLK0 F32B1 F33B1 F42B1 F43B1 +CLK1 F32B1 F42B1 +CLK2 F33B1 F43B1 +CLK3 - +NONE - + +.config_enum MULT18_1.REG_INPUTC_CLK CLK3 +CLK0 F30B1 F31B1 +CLK1 F30B1 +CLK2 F31B1 +CLK3 - +NONE - + +.config_enum MULT18_1.REG_OUTPUT_CLK CLK3 +CLK0 F3B1 F4B1 F5B1 F6B1 +CLK1 F3B1 F5B1 +CLK2 F4B1 F6B1 +CLK3 - +NONE - + +.config_enum MULT18_1.REG_PIPELINE_CLK CLK3 +CLK0 F13B1 F14B1 F16B1 F17B1 +CLK1 F13B1 F16B1 +CLK2 F14B1 F17B1 +CLK3 - +NONE - + +.config_enum MULT18_1.RESETMODE SYNC +ASYNC F2B1 F12B1 +SYNC - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP4/bits.db b/ECP5/tiledata/MIB2_DSP4/bits.db index 874b5c7..1c884bd 100644 --- a/ECP5/tiledata/MIB2_DSP4/bits.db +++ b/ECP5/tiledata/MIB2_DSP4/bits.db
@@ -66,5 +66,51 @@ CE2 F8B1 F26B1 F30B1 F36B1 CE3 - +.config_enum MULT18_1.REG_PIPELINE_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F0B1 F5B1 + +.config_enum MULT18_4.REG_PIPELINE_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F80B1 F83B1 + +.config_enum MULT18_5.REG_INPUTA_CE CE3 +CE0 F56B1 F57B1 F81B1 F82B1 F84B1 F85B1 F90B1 F91B1 F97B1 +CE1 F57B1 F82B1 F85B1 F91B1 +CE2 F56B1 F81B1 F84B1 F90B1 F97B1 +CE3 - + +.config_enum MULT18_5.REG_INPUTB_CE CE3 +CE0 F55B1 F58B1 F59B1 F62B1 F63B1 +CE1 F55B1 F59B1 F63B1 +CE2 F58B1 F62B1 +CE3 - + +.config_enum MULT18_5.REG_INPUTC_CLK NONE +CLK0 F60B1 F61B1 +CLK1 F60B1 F61B1 +CLK2 F60B1 F61B1 +CLK3 F60B1 F61B1 +NONE - + +.config_enum MULT18_5.REG_OUTPUT_CLK NONE +CLK0 F92B1 F94B1 F95B1 F96B1 +CLK1 F92B1 F94B1 F95B1 F96B1 +CLK2 F92B1 F94B1 F95B1 F96B1 +CLK3 F92B1 F94B1 F95B1 F96B1 +NONE - + +.config_enum MULT18_5.REG_PIPELINE_CE CE3 +CE0 F86B1 F87B1 F88B1 F89B1 +CE1 F87B1 F89B1 +CE2 F86B1 F88B1 +CE3 - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP5/bits.db b/ECP5/tiledata/MIB2_DSP5/bits.db index d13466e..d0bc3e3 100644 --- a/ECP5/tiledata/MIB2_DSP5/bits.db +++ b/ECP5/tiledata/MIB2_DSP5/bits.db
@@ -1,5 +1,57 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_4.REG_INPUTA_RST RST3 +RST0 F100B1 F101B1 +RST1 F101B1 +RST2 F100B1 +RST3 - + +.config_enum MULT18_4.REG_PIPELINE_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F22B1 F27B1 + +.config_enum MULT18_4.RESETMODE SYNC +ASYNC F93B1 +SYNC - + +.config_enum MULT18_5.REG_INPUTA_CE CE3 +CE0 F39B1 +CE1 F39B1 +CE2 - +CE3 - + +.config_enum MULT18_5.REG_INPUTA_RST RST3 +RST0 F102B1 F103B1 +RST1 F103B1 +RST2 F102B1 +RST3 - + +.config_enum MULT18_5.REG_INPUTB_CE CE3 +CE0 F64B1 +CE1 - +CE2 F64B1 +CE3 - + +.config_enum MULT18_5.REG_PIPELINE_CE CE3 +CE0 F47B1 F65B1 F67B1 F68B1 +CE1 F47B1 F67B1 +CE2 F65B1 F68B1 +CE3 - + +.config_enum MULT18_5.REG_PIPELINE_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F30B1 F32B1 + +.config_enum MULT18_5.RESETMODE SYNC +ASYNC F86B1 F104B1 +SYNC - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP6/bits.db b/ECP5/tiledata/MIB2_DSP6/bits.db index d13466e..41ad503 100644 --- a/ECP5/tiledata/MIB2_DSP6/bits.db +++ b/ECP5/tiledata/MIB2_DSP6/bits.db
@@ -1,5 +1,112 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_4.MODE NONE +MULT18X18D F18B0 F33B1 F37B0 F48B0 F55B0 F67B0 +NONE - + +.config_enum MULT18_4.REG_INPUTA_CLK CLK3 +CLK0 F24B1 F25B1 F34B1 F35B1 F72B1 F73B1 +CLK1 F25B1 F35B1 F73B1 +CLK2 F24B1 F34B1 F72B1 +CLK3 - +NONE - + +.config_enum MULT18_4.REG_INPUTA_RST RST3 +RST0 F14B1 F22B1 F100B1 F101B1 +RST1 F22B1 F101B1 +RST2 F14B1 F100B1 +RST3 - + +.config_enum MULT18_4.REG_INPUTB_CLK CLK3 +CLK0 F36B1 F37B1 F38B1 F39B1 F74B1 F75B1 +CLK1 F37B1 F39B1 F75B1 +CLK2 F36B1 F38B1 F74B1 +CLK3 - +NONE - + +.config_enum MULT18_4.REG_INPUTB_RST RST3 +RST0 F2B1 F3B1 F26B1 F27B1 +RST1 F3B1 F27B1 +RST2 F2B1 F26B1 +RST3 - + +.config_enum MULT18_4.REG_INPUTC_CLK NONE +CLK0 F40B1 F42B1 F46B1 F47B1 +CLK1 F42B1 F46B1 F47B1 +CLK2 F40B1 F46B1 F47B1 +CLK3 F46B1 F47B1 +NONE - + +.config_enum MULT18_4.REG_OUTPUT_CLK CLK3 +CLK0 F62B1 F63B1 F64B1 F65B1 +CLK1 F63B1 F65B1 +CLK2 F62B1 F64B1 +CLK3 - +NONE - + +.config_enum MULT18_4.REG_OUTPUT_RST RST3 +RST0 F78B1 F79B1 F88B1 F89B1 +RST1 F79B1 F89B1 +RST2 F78B1 F88B1 +RST3 - + +.config_enum MULT18_4.REG_PIPELINE_CLK CLK3 +CLK0 F44B1 F45B1 F60B1 F61B1 F76B1 F77B1 F84B1 F85B1 +CLK1 F45B1 F61B1 F77B1 F85B1 +CLK2 F44B1 F60B1 F76B1 F84B1 +CLK3 - +NONE - + +.config_enum MULT18_4.REG_PIPELINE_RST RST3 +RST0 F54B1 F55B1 F66B1 F67B1 +RST1 F55B1 F67B1 +RST2 F54B1 F66B1 +RST3 - + +.config_enum MULT18_4.RESETMODE SYNC +ASYNC F6B1 F18B1 F30B1 F43B1 F50B1 F58B1 F70B1 F82B1 F92B1 F104B1 +SYNC - + +.config_enum MULT18_5.MODE NONE +MULT18X18D F18B0 F23B1 F37B0 F48B0 F55B0 F67B0 +NONE - + +.config_enum MULT18_5.REG_INPUTA_RST RST3 +RST0 F16B1 F17B1 F56B1 F57B1 F68B1 F69B1 +RST1 F17B1 F57B1 F69B1 +RST2 F16B1 F56B1 F68B1 +RST3 - + +.config_enum MULT18_5.REG_INPUTB_RST RST3 +RST0 F4B1 F5B1 F28B1 F29B1 +RST1 F5B1 F29B1 +RST2 F4B1 F28B1 +RST3 - + +.config_enum MULT18_5.REG_INPUTC_CLK NONE +CLK0 F48B1 F49B1 +CLK1 F48B1 F49B1 +CLK2 F48B1 F49B1 +CLK3 F48B1 F49B1 +NONE - + +.config_enum MULT18_5.REG_OUTPUT_CLK NONE +CLK0 F102B1 F103B1 +CLK1 F102B1 F103B1 +CLK2 F102B1 F103B1 +CLK3 F102B1 F103B1 +NONE - + +.config_enum MULT18_5.REG_PIPELINE_RST RST3 +RST0 F80B1 F81B1 F90B1 F91B1 +RST1 F81B1 F91B1 +RST2 F80B1 F90B1 +RST3 - + +.config_enum MULT18_5.RESETMODE SYNC +ASYNC F7B1 F19B1 F31B1 F51B1 F59B1 F71B1 F83B1 F93B1 F105B1 +SYNC - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP7/bits.db b/ECP5/tiledata/MIB2_DSP7/bits.db index d13466e..98e5c91 100644 --- a/ECP5/tiledata/MIB2_DSP7/bits.db +++ b/ECP5/tiledata/MIB2_DSP7/bits.db
@@ -1,5 +1,86 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_4.MODE NONE +MULT18X18D F29B0 F30B0 F32B0 F83B0 +NONE - + +.config_enum MULT18_4.REG_INPUTB_RST RST3 +RST0 F2B1 F3B1 +RST1 F3B1 +RST2 F2B1 +RST3 - + +.config_enum MULT18_4.REG_PIPELINE_RST RST3 +RST0 F6B1 F7B1 F18B1 F19B1 +RST1 F7B1 F19B1 +RST2 F6B1 F18B1 +RST3 - + +.config_enum MULT18_4.RESETMODE SYNC +ASYNC F0B1 F10B1 F34B1 F46B1 +SYNC - + +.config_enum MULT18_5.MODE NONE +MULT18X18D F29B0 F30B0 F32B0 F83B0 +NONE - + +.config_enum MULT18_5.REG_INPUTA_CLK CLK3 +CLK0 F41B1 F48B1 F68B1 F69B1 F74B1 F75B1 F88B1 F89B1 F100B1 F101B1 +CLK1 F41B1 F68B1 F74B1 F88B1 F100B1 +CLK2 F48B1 F69B1 F75B1 F89B1 F101B1 +CLK3 - +NONE - + +.config_enum MULT18_5.REG_INPUTA_RST RST3 +RST0 F8B1 F9B1 +RST1 F9B1 +RST2 F8B1 +RST3 - + +.config_enum MULT18_5.REG_INPUTB_CLK CLK3 +CLK0 F38B1 F40B1 F84B1 F85B1 F94B1 F95B1 +CLK1 F38B1 F84B1 F94B1 +CLK2 F40B1 F85B1 F95B1 +CLK3 - +NONE - + +.config_enum MULT18_5.REG_INPUTB_RST RST3 +RST0 F20B1 F21B1 +RST1 F21B1 +RST2 F20B1 +RST3 - + +.config_enum MULT18_5.REG_INPUTC_CLK CLK3 +CLK0 F80B1 F81B1 +CLK1 F80B1 +CLK2 F81B1 +CLK3 - +NONE - + +.config_enum MULT18_5.REG_OUTPUT_CLK NONE +CLK0 F4B1 F5B1 F49B1 F57B1 F58B1 F59B1 +CLK1 F4B1 F5B1 F49B1 F58B1 +CLK2 F4B1 F5B1 F57B1 F59B1 +CLK3 F4B1 F5B1 +NONE - + +.config_enum MULT18_5.REG_PIPELINE_CLK CLK3 +CLK0 F28B1 F29B1 F36B1 F37B1 F60B1 F61B1 F63B1 F67B1 +CLK1 F28B1 F36B1 F60B1 F67B1 +CLK2 F29B1 F37B1 F61B1 F63B1 +CLK3 - +NONE - + +.config_enum MULT18_5.REG_PIPELINE_RST RST3 +RST0 F32B1 F33B1 F44B1 F45B1 +RST1 F33B1 F45B1 +RST2 F32B1 F44B1 +RST3 - + +.config_enum MULT18_5.RESETMODE SYNC +ASYNC F1B1 F11B1 F23B1 F35B1 F39B1 F66B1 +SYNC - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB2_DSP8/bits.db b/ECP5/tiledata/MIB2_DSP8/bits.db index d13466e..9349143 100644 --- a/ECP5/tiledata/MIB2_DSP8/bits.db +++ b/ECP5/tiledata/MIB2_DSP8/bits.db
@@ -1,5 +1,44 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_4.REG_INPUTA_CE CE3 +CE0 F54B1 F55B1 F68B1 F69B1 F91B1 F92B1 +CE1 F54B1 F68B1 F92B1 +CE2 F55B1 F69B1 F91B1 +CE3 - + +.config_enum MULT18_4.REG_INPUTB_CE CE3 +CE0 F51B1 F65B1 F83B1 F84B1 F89B1 F90B1 +CE1 F65B1 F84B1 F90B1 +CE2 F51B1 F83B1 F89B1 +CE3 - + +.config_enum MULT18_4.REG_INPUTC_CLK NONE +CLK0 F63B1 F64B1 +CLK1 F63B1 F64B1 +CLK2 F63B1 F64B1 +CLK3 F63B1 F64B1 +NONE - + +.config_enum MULT18_4.REG_OUTPUT_CLK NONE +CLK0 F49B1 F66B1 F87B1 F88B1 +CLK1 F49B1 F66B1 F87B1 F88B1 +CLK2 F49B1 F66B1 F87B1 F88B1 +CLK3 F49B1 F66B1 F87B1 F88B1 +NONE - + +.config_enum MULT18_4.REG_PIPELINE_CE CE3 +CE0 F61B1 F62B1 F77B1 F78B1 F81B1 F82B1 F85B1 F86B1 +CE1 F62B1 F78B1 F82B1 F86B1 +CE2 F61B1 F77B1 F81B1 F85B1 +CE3 - + +.config_enum MULT18_5.REG_PIPELINE_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F50B1 F58B1 + # Fixed Connections
diff --git a/ECP5/tiledata/MIB_DSP1/bits.db b/ECP5/tiledata/MIB_DSP1/bits.db index 64f7c29..48faed4 100644 --- a/ECP5/tiledata/MIB_DSP1/bits.db +++ b/ECP5/tiledata/MIB_DSP1/bits.db
@@ -16,6 +16,10 @@ DISABLED F61B0 ENABLED - +.config_enum MULT18_1.GSR ENABLED +DISABLED F61B0 +ENABLED - + # Fixed Connections .fixed_conn E1_JMB0_ALU24 JP0_MULT9
diff --git a/ECP5/tiledata/MIB_DSP2/bits.db b/ECP5/tiledata/MIB_DSP2/bits.db index cdc067a..bd087e5 100644 --- a/ECP5/tiledata/MIB_DSP2/bits.db +++ b/ECP5/tiledata/MIB_DSP2/bits.db
@@ -382,6 +382,47 @@ CLK3 - NONE F58B0 +.config_enum MULT18_1.CLK0_DIV ENABLED +DISABLED F65B0 +ENABLED - + +.config_enum MULT18_1.CLK1_DIV ENABLED +DISABLED F66B0 +ENABLED - + +.config_enum MULT18_1.CLK2_DIV ENABLED +DISABLED F67B0 +ENABLED - + +.config_enum MULT18_1.CLK3_DIV ENABLED +DISABLED F68B0 +ENABLED - + +.config_enum MULT18_1.GSR ENABLED +DISABLED F60B0 +ENABLED - + +.config_enum MULT18_1.REG_INPUTA_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F27B0 F28B0 F35B0 + +.config_enum MULT18_1.REG_INPUTB_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F20B0 + +.config_enum MULT18_1.REG_INPUTC_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F59B0 + # Fixed Connections .fixed_conn E1_JC0_ALU54 JDSPC0
diff --git a/ECP5/tiledata/MIB_DSP4/bits.db b/ECP5/tiledata/MIB_DSP4/bits.db index 361a590..d7bf301 100644 --- a/ECP5/tiledata/MIB_DSP4/bits.db +++ b/ECP5/tiledata/MIB_DSP4/bits.db
@@ -59,5 +59,24 @@ ALU54B F34B0 F41B0 NONE - +.config_enum MULT18_1.REG_INPUTB_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F34B0 F41B0 + +.config_enum MULT18_1.SOURCEB_MODE +B_C_DYNAMIC F32B0 +B_SHIFT F29B0 +C_SHIFT F28B0 F29B0 +HIGHSPEED F28B0 F32B0 + +.config_enum MULT18_4.SOURCEB_MODE +B_C_DYNAMIC F91B0 +B_SHIFT F92B0 +C_SHIFT F90B0 F92B0 +HIGHSPEED F90B0 F91B0 + # Fixed Connections
diff --git a/ECP5/tiledata/MIB_DSP5/bits.db b/ECP5/tiledata/MIB_DSP5/bits.db index d13466e..08a31cb 100644 --- a/ECP5/tiledata/MIB_DSP5/bits.db +++ b/ECP5/tiledata/MIB_DSP5/bits.db
@@ -1,5 +1,33 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_4.REG_INPUTA_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F10B0 F11B0 + +.config_enum MULT18_4.REG_INPUTB_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F7B0 F63B0 + +.config_enum MULT18_4.REG_INPUTC_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F57B0 + +.config_enum MULT18_5.REG_INPUTC_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F56B0 + # Fixed Connections
diff --git a/ECP5/tiledata/MIB_DSP6/bits.db b/ECP5/tiledata/MIB_DSP6/bits.db index d13466e..ea6e499 100644 --- a/ECP5/tiledata/MIB_DSP6/bits.db +++ b/ECP5/tiledata/MIB_DSP6/bits.db
@@ -1,5 +1,34 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_4.GSR ENABLED +DISABLED F46B0 +ENABLED - + +.config_enum MULT18_4.REG_INPUTB_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F87B0 + +.config_enum MULT18_5.GSR ENABLED +DISABLED F46B0 +ENABLED - + +.config_enum MULT18_5.REG_INPUTA_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F80B0 F81B0 F88B0 + +.config_enum MULT18_5.REG_INPUTB_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F73B0 + # Fixed Connections
diff --git a/ECP5/tiledata/MIB_DSP7/bits.db b/ECP5/tiledata/MIB_DSP7/bits.db index d13466e..0c86e65 100644 --- a/ECP5/tiledata/MIB_DSP7/bits.db +++ b/ECP5/tiledata/MIB_DSP7/bits.db
@@ -1,5 +1,52 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_4.CLK0_DIV ENABLED +DISABLED F9B0 +ENABLED - + +.config_enum MULT18_4.CLK1_DIV ENABLED +DISABLED F10B0 +ENABLED - + +.config_enum MULT18_4.CLK2_DIV ENABLED +DISABLED F11B0 +ENABLED - + +.config_enum MULT18_4.CLK3_DIV ENABLED +DISABLED F12B0 +ENABLED - + +.config_enum MULT18_4.GSR ENABLED +DISABLED F4B0 +ENABLED - + +.config_enum MULT18_4.REG_INPUTA_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F1B0 + +.config_enum MULT18_5.CLK0_DIV ENABLED +DISABLED F9B0 +ENABLED - + +.config_enum MULT18_5.CLK1_DIV ENABLED +DISABLED F10B0 +ENABLED - + +.config_enum MULT18_5.CLK2_DIV ENABLED +DISABLED F11B0 +ENABLED - + +.config_enum MULT18_5.CLK3_DIV ENABLED +DISABLED F12B0 +ENABLED - + +.config_enum MULT18_5.GSR ENABLED +DISABLED F4B0 +ENABLED - + # Fixed Connections
diff --git a/ECP5/tiledata/MIB_DSP8/bits.db b/ECP5/tiledata/MIB_DSP8/bits.db index d13466e..c4b7cd6 100644 --- a/ECP5/tiledata/MIB_DSP8/bits.db +++ b/ECP5/tiledata/MIB_DSP8/bits.db
@@ -1,5 +1,18 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum MULT18_5.REG_INPUTB_CLK CLK3 +CLK0 - +CLK1 - +CLK2 - +CLK3 - +NONE F55B0 F61B0 + +.config_enum MULT18_5.SOURCEB_MODE +B_C_DYNAMIC F51B0 +B_SHIFT F60B0 +C_SHIFT F59B0 F60B0 +HIGHSPEED F51B0 F59B0 + # Fixed Connections