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foss-fpga-tools
/
prjtrellis
/
0b3c6be1a2936d07dca96ce7d184c513d59dee0d
/
.
/
minitests
/
reg
/
ce.v
blob: bb4c05b3ad2db0db89ce64ea16afede775f76130 [
file
]
module
top
(
input clk
,
input d
,
cen
,
output reg q
);
always
@(
posedge clk
)
if
(
cen
)
q
<=
d
;
endmodule
