Sign in
foss-fpga-tools
/
prjtrellis
/
200893d7641c37c9fdeff92ce1e12233be14d53f
/
.
/
minitests
/
wire
/
wire.v
blob: 13bed6fab0596aab7678f5e2cb428863c496f1bd [
file
]
module
top
(
input a
,
output q
);
assign q
=
a
;
endmodule
