libtrellis/tests/testdata/test/tiledata/TESTTILE/bits.db

.mux A0
H0 F0B0 F0B2
H1 F0B1 F0B2
H2 F0B0 F0B3
Q0 F0B1 F0B3

.config INIT 1111
!F1B0
!F1B1
!F1B2
!F1B3

.config_enum MODE LOGIC
LOGIC
CARRY F2B0
DPRAM F2B1