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foss-fpga-tools
/
prjtrellis
/
2f06397673bbca3da11928d538b8ab7d01c944c6
/
.
/
minitests
/
ECP5
/
dsp
/
mult.v
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module
top
(
input
[
17
:
0
]
a
,
input
[
17
:
0
]
b
,
input
[
35
:
0
]
c
,
output
[
35
:
0
]
q
);
(*
syn_multstyle
=
"block_mult"
*)
wire
[
35
:
0
]
product
=
a
*
b
;
assign q
=
product
+
c
;
endmodule