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foss-fpga-tools
/
prjtrellis
/
2f06397673bbca3da11928d538b8ab7d01c944c6
/
.
/
minitests
/
lut
/
lut.v
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module
top
(
input a
,
input b
,
input c
,
input d
,
output q
);
assign q
=
a
&
b
&
c
&
d
;
endmodule