Add LS0/RS0 tile fixed connection fuzzing.
diff --git a/fuzzers/machxo2/050-pio_routing/fuzzer.py b/fuzzers/machxo2/050-pio_routing/fuzzer.py index 214908c..7dd07c2 100644 --- a/fuzzers/machxo2/050-pio_routing/fuzzer.py +++ b/fuzzers/machxo2/050-pio_routing/fuzzer.py
@@ -58,6 +58,8 @@ "missing_nets" : None, "bank" : "L" }, + + # 4 { "pos" : (10, 22), "cfg" : FuzzConfig(job="PIOROUTER", family="MachXO2", device="LCMXO2-1200HC", ncl="pioroute.ncl", @@ -79,6 +81,22 @@ "missing_nets" : None, "bank" : None, }, + { + "pos" : (9, 1), + "cfg" : FuzzConfig(job="PIOROUTELS0", family="MachXO2", device="LCMXO2-1200HC", ncl="pioroute.ncl", + tiles=["PL9:PIC_LS0"]), + "missing_nets" : None, + "bank" : "LS", + }, + + # 8 + { + "pos" : (3, 22), + "cfg" : FuzzConfig(job="PIOROUTERS0", family="MachXO2", device="LCMXO2-1200HC", ncl="pioroute.ncl", + tiles=["PR3:PIC_RS0"]), + "missing_nets" : None, + "bank" : "RS", + }, ] def main(args): @@ -108,10 +126,12 @@ if args.p and job["bank"]: # I/O connections in the left/right tiles exist as-if a column "0" # or one past maximum is physically present. - if job["bank"] == "R": - io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] + 1), job["bank"]) - elif job["bank"] == "L": - io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] - 1), job["bank"]) + if job["bank"].startswith("R"): + ab_only = job["bank"].endswith("S") + io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] + 1), job["bank"], ab_only) + elif job["bank"].startswith("L"): + ab_only = job["bank"].endswith("S") + io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] - 1), job["bank"], ab_only) else: io_nets = mk_nets.io_conns(job["pos"][0], job["bank"])
diff --git a/fuzzers/machxo2/050-pio_routing/mk_nets.py b/fuzzers/machxo2/050-pio_routing/mk_nets.py index 308b667..8648e26 100644 --- a/fuzzers/machxo2/050-pio_routing/mk_nets.py +++ b/fuzzers/machxo2/050-pio_routing/mk_nets.py
@@ -3,7 +3,7 @@ from collections import defaultdict import re -def io_conns(tile, bank): +def io_conns(tile, bank, ab_only=False): # All I/O connections on the left bank are contained in the other banks. all_template = [ ("JPADDO{}", "sink"), @@ -55,7 +55,7 @@ bank_template = bottom elif bank == "T": bank_template = top - elif bank == "R": + elif bank.startswith("R"): bank_template = right else: bank_template = [] @@ -69,7 +69,12 @@ eclk_re = re.compile("ECLKC*") netlist = [] - for pad in ("A", "B", "C", "D"): + if ab_only: + pads = ("A", "B") + else: + pads = ("A", "B", "C", "D") + + for pad in pads: # B/BS/T/TSIOLOGIC if bank in ("B", "T"): if pad == "A": @@ -79,7 +84,7 @@ else: io_prefix = "" # RIOLOGIC - elif bank == "R": + elif bank.startswith("R"): io_prefix = "R" # Just "LOGIC" else: @@ -89,7 +94,7 @@ suffix = f.format(pad, io_prefix) netlist.append(("R{}C{}_{}".format(tile[0], tile[1], suffix), d)) - if bank == "R": + if bank.startswith("R"): for f, d in bank_template: suffix = f.format(pad, io_prefix) netlist.append(("R{}C{}_{}".format(tile[0], tile[1], suffix), d)) @@ -127,11 +132,14 @@ return netlist def main(): - for t, b in zip(((10, 0), (12, 11), (10, 23), (1, 11)), ("L", "B", "R", "T")): - print("Bank {}:".format(b)) - for i, n in enumerate(io_conns(t, b)): - print(i, n) - print("") + for t, b, ab in zip( + ((10, 0), (12, 11), (10, 23), (1, 11), (9, 0), (3, 23)), + ("L", "B", "R", "T", "LS", "RS"), + (False, False, False, False, True, True)): + print("Bank {} (AB only={}):".format(b, ab)) + for i, n in enumerate(io_conns(t, b, ab)): + print(i, n) + print("") if __name__ == "__main__": main()