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foss-fpga-tools
/
prjtrellis
/
5bdc3aa8858f25253ec007b13da3ff6ef136999d
/
.
/
minitests
/
reg
/
ce.v
blob: bb4c05b3ad2db0db89ce64ea16afede775f76130 [
file
]
module
top
(
input clk
,
input d
,
cen
,
output reg q
);
always
@(
posedge clk
)
if
(
cen
)
q
<=
d
;
endmodule
