minitests/reg/lut_reg.v - prjtrellis - Git at Google


            
            module top(input clk, input a, output reg q);

            
            always @(posedge clk)

            
                q <= ~a;

            
            endmodule
	module top(input clk, input a, output reg q);
	always @(posedge clk)
	q <= ~a;
	endmodule