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foss-fpga-tools
/
prjtrellis
/
6eae4a634935b0e49275508196c4dc0c6cf290ef
/
.
/
minitests
/
wire
/
wire_pad.v
blob: 13bed6fab0596aab7678f5e2cb428863c496f1bd [
file
]
module
top
(
input a
,
output q
);
assign q
=
a
;
endmodule
