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foss-fpga-tools
/
prjtrellis
/
7b80d66ab328bcbe44f94fb66939a3c333bc08f3
/
.
/
minitests
/
reg
/
ce.v
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module
top
(
input clk
,
input d
,
cen
,
output reg q
);
always
@(
posedge clk
)
if
(
cen
)
q
<=
d
;
endmodule
