Sign in
foss-fpga-tools
/
prjtrellis
/
7bd73011f2aff1d9780f1dc46edef5610f9ef250
/
.
/
minitests
/
wire
/
wire.v
blob: 13bed6fab0596aab7678f5e2cb428863c496f1bd [
file
] [
log
] [
blame
]
module
top
(
input a
,
output q
);
assign q
=
a
;
endmodule
