Sign in
foss-fpga-tools
/
prjtrellis
/
90910577671cdd950e56df6cb29d848dadea9467
/
.
/
minitests
/
lut
/
lut.v
blob: 2c7266a907cf9fca0c86258c1d58d75c122f74fe [
file
] [
log
] [
blame
]
module
top
(
input a
,
input b
,
input c
,
input d
,
output q
);
assign q
=
a
&
b
&
c
&
d
;
endmodule