minitests/reg/ce_inv.v - prjtrellis - Git at Google

 module top(input clk, input d, cen, output reg q);
     always @(posedge clk)
         if (!cen)
             q <= d;
 endmodule
	module top(input clk, input d, cen, output reg q);
	always @(posedge clk)
	if (!cen)
	q <= d;
	endmodule