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foss-fpga-tools
/
prjtrellis
/
c4c9f0d50da9e7e0919d1b0e99cb46b35e9946d7
/
.
/
minitests
/
wire
/
wire_pad.v
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module
top
(
input a
,
output q
);
assign q
=
a
;
endmodule
