fuzzers: Add a SEDGA fuzzer Signed-off-by: David Shah <dave@ds0.me>

diff --git a/fuzzers/105-sedga/empty.ncl b/fuzzers/105-sedga/empty.ncl
new file mode 100644
index 0000000..a8583f8
--- /dev/null
+++ b/fuzzers/105-sedga/empty.ncl

@@ -0,0 +1,12 @@
+::FROM-WRITER;
+design top
+{
+   device
+   {
+      architecture sa5p00;
+      device LFE5U-45F;
+      package CABGA381;
+      performance "8";
+   }
+
+}

diff --git a/fuzzers/105-sedga/fuzzer.py b/fuzzers/105-sedga/fuzzer.py
new file mode 100644
index 0000000..440cf08
--- /dev/null
+++ b/fuzzers/105-sedga/fuzzer.py

@@ -0,0 +1,54 @@
+from fuzzconfig import FuzzConfig
+import nonrouting
+import pytrellis
+import fuzzloops
+import interconnect
+
+cfg = FuzzConfig(job="JTAG", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
+                                          tiles=["MIB_R71C4:EFB0_PICB0", "MIB_R71C5:EFB1_PICB1", "MIB_R71C6:EFB2_PICB0"])
+
+
+def get_substs(exclk_used="YES", clk_freq="2.4", checkalways="DISABLED"):
+    if clk_freq == "NONE":
+        comment = "//"
+    else:
+        comment = ""
+    if exclk_used == "YES" and clk_freq != "NONE":
+        scomment = ""
+    else:
+        scomment = "//"
+    return dict(comment=comment, scomment=scomment, clk_freq=clk_freq, checkalways=checkalways)
+
+
+def main():
+    pytrellis.load_database("../../database")
+    cfg.setup()
+    empty_bitfile = cfg.build_design(cfg.ncl, {})
+    cfg.ncl = "sed.ncl"
+
+    nonrouting.fuzz_enum_setting(cfg, "SED.CLK_FREQ", ["NONE", "2.4", "4.8", "9.7", "19.4", "38.8", "62.0"],
+                                 lambda x: get_substs(clk_freq=x), empty_bitfile, False)
+    nonrouting.fuzz_enum_setting(cfg, "SED.CHECKALWAYS", ["DISABLED", "ENABLED"],
+                                 lambda x: get_substs(checkalways=x), empty_bitfile, False)
+    nonrouting.fuzz_enum_setting(cfg, "SED.SEDEXCLK_USED", ["YES", "NO"],
+                                 lambda x: get_substs(exclk_used=x), empty_bitfile, False)
+    cfg.ncl = "sed_routing.ncl"
+    interconnect.fuzz_interconnect_with_netnames(
+        cfg,
+        ["R70C4_SEDSTDBY_SED",
+         "R70C4_JSEDENABLE_SED",
+         "R70C4_JSEDSTART_SED",
+         "R70C4_JSEDFRCERR_SED",
+         "R70C4_JSEDEXCLK_SED",
+         "R70C4_JSEDERR_SED",
+         "R70C4_JSEDDONE_SED",
+         "R70C4_JSEDINPROG_SED",
+         "R70C4_JAUTODONE_SED"
+         ],
+        bidir=True
+    )
+
+
+if __name__ == "__main__":
+    main()
+

diff --git a/fuzzers/105-sedga/sed.ncl b/fuzzers/105-sedga/sed.ncl
new file mode 100644
index 0000000..883c5c9
--- /dev/null
+++ b/fuzzers/105-sedga/sed.ncl

@@ -0,0 +1,30 @@
+::FROM-WRITER;
+design top
+{
+   device
+   {
+      architecture sa5p00;
+      device LFE5U-45F;
+      package CABGA381;
+      performance "8";
+   }
+   ${comment} comp SED
+   ${comment} {
+   ${comment}    logical {
+   ${comment}       cellmodel-name SED;
+   ${comment}       program "MODE:SEDGA "
+   ${comment}               "SEDGA:::SED_CLK_FREQ=${clk_freq},CHECKALWAYS=${checkalways}";
+   ${comment}    }
+   ${comment}    site SED;
+   ${comment} }
+
+   ${scomment}  signal q_c
+   ${scomment} {
+   ${scomment}    signal-pins
+   ${scomment}       // drivers
+   ${scomment}       (SED, AUTODONE),
+   ${scomment}       // loads
+   ${scomment}       (SED, SEDEXCLK);
+   ${scomment} }
+
+}

diff --git a/fuzzers/105-sedga/sed_routing.ncl b/fuzzers/105-sedga/sed_routing.ncl
new file mode 100644
index 0000000..11ad1a9
--- /dev/null
+++ b/fuzzers/105-sedga/sed_routing.ncl

@@ -0,0 +1,35 @@
+::FROM-WRITER;
+design top
+{
+   device
+   {
+      architecture sa5p00;
+      device LFE5U-45F;
+      package CABGA381;
+      performance "8";
+   }
+
+   comp SLICE_0
+      [,,,,A0,B0,D0,C0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,]
+   {
+      logical
+      {
+         cellmodel-name SLICE;
+         program "MODE:LOGIC "
+                 "K0::H0=0 "
+                 "F0:F ";
+         primitive K0 i3_4_lut;
+      }
+      site R2C2A;
+   }
+
+    signal q_c
+   {
+      signal-pins
+         // drivers
+         (SLICE_0, F0),
+         // loads
+         (SLICE_0, A0);
+      ${route}
+   }
+}