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foss-fpga-tools
/
prjtrellis
/
dc4120e76750ed372feab637f299585908431c35
/
.
/
minitests
/
dsp
/
preadd.v
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module
top
(
input
[
8
:
0
]
a
,
input
[
8
:
0
]
b
,
input
[
8
:
0
]
c
,
output
[
17
:
0
]
q
);
wire
[
8
:
0
]
add
=
a
+
b
;
(*
syn_multstyle
=
"block_mult"
*)
wire
[
17
:
0
]
res
=
add
*
c
;
assign q
=
res
;
endmodule
