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foss-fpga-tools
/
prjtrellis
/
dc4120e76750ed372feab637f299585908431c35
/
.
/
minitests
/
iologic
/
ireg.v
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module
top
(
input clk
,
input d
,
output q
);
IFS1P3IX ireg_i
(.
D
(
d
),
.
SCLK
(
clk
),
.
SP
(
1
'b1), .CD(1'
b0
),
.
Q
(
q
));
endmodule
