Sign in
foss-fpga-tools
/
prjtrellis
/
dc4120e76750ed372feab637f299585908431c35
/
.
/
minitests
/
reg
/
async.v
blob: 23f921afacdaa4723c99183452333e125cad78fd [
file
] [
log
] [
blame
]
module
top
(
input clk
,
d
,
set
,
output reg q
);
always
@(
posedge clk
or
posedge
set
)
if
(
set
)
q
<=
1
'b1;
else
q <= d;
endmodule