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foss-fpga-tools
/
prjtrellis
/
dc4120e76750ed372feab637f299585908431c35
/
.
/
minitests
/
reg
/
ce_0.v
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module
top
(
input clk
,
input d
,
input r
,
input s
,
output q
);
GSR gsr
(.
GSR
(
r
));
FD1P3JX ff
(.
D
(
d
),
.
SP
(
1
'b0), .PD(s), .CK(clk), .Q(q));
endmodule