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foss-fpga-tools
/
prjtrellis
/
dc4120e76750ed372feab637f299585908431c35
/
.
/
minitests
/
reg
/
ce_over_lsr.v
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module
top
(
input clk
,
d
,
set
,
cen
,
output reg q
);
always
@(
posedge clk
)
if
(
cen
)
if
(
set
)
q
<=
1
'b1;
else
q <= d;
endmodule
