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foss-fpga-tools
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prjtrellis
/
dc4120e76750ed372feab637f299585908431c35
/
.
/
minitests
/
reg
/
plain.v
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module
top
(
input clk
,
input d
,
output reg q
);
always
@(
posedge clk
)
q
<=
d
;
endmodule