Do not place IO BELs at CIB tiles.

libtrellis/src/Chip.cpp

diff --git a/libtrellis/src/Chip.cpp b/libtrellis/src/Chip.cpp
index 60341f7..ce51a52 100644
--- a/libtrellis/src/Chip.cpp
+++ b/libtrellis/src/Chip.cpp
@@ -291,13 +291,19 @@
                 MachXO2Bels::add_lc(*rg, x, y, z);
 
         // PIO Bels
-        if (tile->info.type.find("DUMMY") == string::npos && (tile->info.type.find("PIC_L0") != string::npos ||
-            tile->info.type.find("PIC_LS0") != string::npos || tile->info.type.find("PIC_T") != string::npos ||
-            tile->info.type.find("PIC_R0") != string::npos || tile->info.type.find("PIC_RS0") != string::npos ||
-            tile->info.type.find("PIC_B") != string::npos))
+        // DUMMY and CIB tiles can have the below strings and can possibly
+        // have BELs. But they will not have PIO BELs.
+        if (tile->info.type.find("DUMMY") == string::npos && tile->info.type.find("CIB") == string::npos &&
+            (tile->info.type.find("PIC_L0") != string::npos || tile->info.type.find("PIC_T") != string::npos ||
+             tile->info.type.find("PIC_R0") != string::npos || tile->info.type.find("PIC_B") != string::npos))
             for (int z = 0; z < 4; z++)
                 MachXO2Bels::add_pio(*rg, x, y, z);
 
+        // Single I/O pair.
+        if (tile->info.type.find("PIC_LS0") != string::npos || tile->info.type.find("PIC_RS0") != string::npos)
+            for (int z = 0; z < 2; z++)
+                MachXO2Bels::add_pio(*rg, x, y, z);
+
         // DCC/DCM Bels
         if (tile->info.type.find("CENTER_EBR_CIB") != string::npos) {
           for (int z = 0; z < 8; z++)